<html><body><p> <pre> On Fri, 2025-01-10 at 14:01 +0100, Krzysztof Kozlowski wrote: > > External email : Please do not click links or open attachments until > you have verified the sender or the content. > > > On 10/01/2025 13:33, paul-pl.chen wrote: > > From: "Paul-pl.Chen" <paul-pl.chen@mediatek.com> > > > > Add mediatek,exdma.yaml to support EXDMA for MT8196. > > > > Signed-off-by: Paul-pl.Chen <paul-pl.chen@mediatek.com> > > --- > > The header used in examples: > > #include <dt-bindings/clock/mt8196-clk.h> > > #include <dt-bindings/power/mt8196-power.h> > > are not upstreamed yet. > > Which makes this untestable and unmergeable. > > This cannot be accepted. Fix your dependencies or decouple from them. > > > It will be sent by related owner soon. > > Still this won't build and won't be possible to apply. > > > --- > > .../display/mediatek/mediatek,exdma.yaml | 77 > > +++++++++++++++++++ > > 1 file changed, 77 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,exdma.y > > aml > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,exdma > > .yaml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,exdma > > .yaml > > new file mode 100644 > > index 000000000000..385f5549dfaa > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,exdma > > .yaml > > Filename matching compatible. > > Why is this in display? DMA goes to dma. Hi Krzysztof , Regarding the issue of the EXDMA driver, we have conducted an internal survey of drivers under the DMA subsystem. We found that EXDMA operates differently from typical DMA drivers, and therefore we believe that the EXDMA driver may not be suitable to be placed under the driver/mediatek/drm directory. The main reasons are as follows: (1)No Memory Allocation within EXDMA Engine: The EXDMA engine does not perform memory allocation operations itself. Instead, it relies on GEM (Graphics Execution Manager) to allocate memory.Traditional DMA drivers often handle their own memory allocations, but in the case of EXDMA, memory management is delegated to GEM. (2)Primary Task of EXDMA: The main function of EXDMA is to transfer buffers allocated by GEM to the subsequent display pipeline. EXDMA serves as a bridge between memory allocated by GEM and the display components, rather than acting as a general-purpose DMA engine. Based on the points above, we have decided to place the EXDMA driver under the DRM display subsystem rather than under the DMA subsystem. > > > @@ -0,0 +1,77 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,exdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!ldlqohpAoMyTt24UKnssKOk5Qvmc_wlvQPCdjneKDCeshDPwI5Uuuy4A2sI2RlfYLIFDKZx_-GGDOlX48Q$ > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!ldlqohpAoMyTt24UKnssKOk5Qvmc_wlvQPCdjneKDCeshDPwI5Uuuy4A2sI2RlfYLIFDKZx_-GHpxO9DFQ$ > > + > > +title: MediaTek EXDMA > > + > > +maintainers: > > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > > + - Philipp Zabel <p.zabel@pengutronix.de> > > + > > +description: > > + The MediaTek display overlap extended DMA engine, namely > > OVL_EXDMA or EXDMA, > > + primarily functions as a DMA engine for reading data from DRAM > > with various > > + DRAM footprints and data formats. For input sources in certain > > color formats > > + and color domains, OVL_EXDMA also includes a color transfer > > function > > + to process pixels into a consistent color domain. > > + > > Missing ref to dma schemas. allOf: - $ref: dma-controller.yaml# > > > +properties: > > + compatible: > > + const: mediatek,mt8196-exdma > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + items: > > + - description: EXDMA Clock > > + > > + power-domains: > > + maxItems: 1 > > + > > + mediatek,larb: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > Why array? And isn't the property named mediatek,larbs? > Using "mediatek,larb" here is correct because the EXDMA hardware IP will only have one mediatek,larb. In the next version, we will change the phandle-array definition to a single phandle. Please refer to this link: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/Documentation/devicetree/bindings?id=6d0990e6e844cfa045b1a7348f58964caceb4de4 Since MT8196 use SMMU, the SMMU can no longer internally determine the connection relationship between smi-larb and the consumer's pm_runtime_get(_sync). Therefore, we need to add this information back. > > > > > > Best, Paul </pre> </p></body></html><pre>************* MEDIATEK Confidentiality Notice ******************** The information contained in this e-mail message (including any attachments) may be confidential, proprietary, privileged, or otherwise exempt from disclosure under applicable laws. It is intended to be conveyed only to the designated recipient(s). Any use, dissemination, distribution, printing, retaining or copying of this e-mail (including its attachments) by unintended recipient(s) is strictly prohibited and may be unlawful. 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