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On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
> Add MDP-RSZ hardware description for MediaTek MT8196 SoC
>
> Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> ---
> .../display/mediatek/mediatek,mdp-rsz.yaml | 46 +++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml
> new file mode 100644
> index 000000000000..6642b9aa651a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rsz.yaml*__;Iw!!CTRNKA9wMg0ARbw!jo9-Ezn5GR8wfDCMX72zrrpxlMEYb-5w52TYinNWsQlfpiPjw5R967JIU0-6WnI5fvIU7-v0IVaRALBlW4aL$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jo9-Ezn5GR8wfDCMX72zrrpxlMEYb-5w52TYinNWsQlfpiPjw5R967JIU0-6WnI5fvIU7-v0IVaRAIIMW8TJ$
> +
> +title: MediaTek display multimedia data path resizer
> +
> +maintainers:
> + - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> + - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> + MediaTek display multimedia data path resizer, namely MDP-RSZ,
> + can do scaling up/down to the picture.
> +
> +properties:
> + compatible:
> + const: mediatek,mt8196-disp-mdp-rsz
Reference to other display mdp device compatible, use
mediatek,mt8196-mdp-rsz
Regards,
CK
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: MDP-RSZ Clock
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + disp_mdp_rsz0: disp-mdp-rsz0@321a0000 {
> + compatible = "mediatek,mt8196-disp-mdp-rsz";
> + reg = <0 0x321a0000 0 0x1000>;
> + clocks = <&dispsys_config_clk 101>;
> + };
> + };
</pre>
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