[PATCH V5 23/25] drm/etnaviv: do not enable debug registers unconditionally

[Lucas Stach]

Am Sonntag, den 24.09.2017, 15:15 +0200 schrieb Christian Gmeiner:
> Everytime etnaviv_gpu_update_clock(..) gets call it overwrittes
> the the complete VIVS_HI_CLOCK_CONTROL register. Instead read
> the register, change scaling value and write the new value.
> 
> Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
> ---
>  drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> index cfe6c76d077e..10a6485a2401 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> @@ -421,8 +421,9 @@ static void etnaviv_gpu_update_clock(struct
> etnaviv_gpu *gpu)
>  			     gpu->base_rate_shader >> gpu-
> >freq_scale);
>  	} else {
>  		unsigned int fscale = 1 << (6 - gpu->freq_scale);
> -		u32 clock =
> VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
> +		u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
>  
> +		clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);

So now you keep the old FSCALE value and additionally set the new one.
This needs to mask out the old value first.

If you don't mind I'll fix this up while applying.

Regards,
Lucas
>  		etnaviv_gpu_load_clock(gpu, clock);
>  	}
>  }