AW:AW: hang check triggered at low temperatures

[Sven Schmitt]

> Am Dienstag, den 05.06.2018, 13:04 +0000 schrieb Sven Schmitt:
> > Hi Lucas,
> >
> > > Hi Sven,
> > >
> > > Am Montag, den 04.06.2018, 06:31 +0000 schrieb Sven Schmitt:
> > > > Hello,
> > > >
> > > > we have discovered a sneaky, temperature based problem in the
> > > > imx6
> > > > etnaviv driver.
> > > >
> > > > If the chip temperature falls bellow 10 degrees celsius and
> > > > display
> > > > update rate raises above 200ms the etnaviv gpu hang check is
> > > > triggered reproducible [1].
> > > > We have the suspicion that the runtime pm autosuspend mechanism
> > > > (configured to 200ms [2]) is the root of the problem.
> > > > Disabling CONFIG_PM heals the bug.
> > >
> > > My guess would be that this isn't directly related to the GPU or
> > > it's
> > > driver, but a bug in the power gating. To confirm/dismiss my
> > > suspicion
> > > you may change imx6_pm_domain_power_off() in drivers/soc/imx/gpc.c
> > > to
> > > always return -EBUSY early to prevent the domain from being power
> > > gated.
> >
> > You're right. I've set "err009619_present = true" in "struct
> > imx_gpc_dt_data imx6q_dt_data" which has the same effect.
> > Is this a appropriate solution for the problem?
> 
> This is a workaround at best.
> My guess is that the power up sequencing takes a bit longer in your
> case. Can you check if manually adjusting the delay in
> imx6_pm_domain_power_on() to wait a bit longer before the clocks are
> switched off make any difference?

You're right again. A delay of 10µs made it work (i've also tried 2µs). 
Is there a race between clk_disable_unprepare() in imx6_pm_domain_power_on()
and etnaviv_gpu_clk_enable() in etnaviv_gpu_clk_enable() 
or what's the root of the problem?

Reading the code i noticed another abnormality: 
in imx6_pm_domain_power_off() the GPC_PGC_PUPSCR register is read 
to determine iso & iso2sw. 
IMHO GPC_PGC_PDNSCR shall be read, right? 
But this shouldn't change anything because the sum stays below 66 
and the result is rounded up to 1µs.

Best regards,
Sven