[Freedreno] [PATCH] freedreno/ir3: add TXF support

[Ilia Mirkin]

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---

Should be moderately easy to test... enable GL3 and run with -t texelFetch.
This still doesn't support offsets, those should get added in separately.
No idea what to put in .y for 1d array, so just guessing 0.

 src/gallium/drivers/freedreno/ir3/ir3_compiler.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
index c6026bb..8f1b55a 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
@@ -1126,6 +1126,7 @@ fill_tex_info(struct ir3_compile_context *ctx,
 	case TGSI_OPCODE_TXB:
 	case TGSI_OPCODE_TXB2:
 	case TGSI_OPCODE_TXL:
+	case TGSI_OPCODE_TXF:
 		info->args = 2;
 		break;
 	case TGSI_OPCODE_TXP:
@@ -1229,11 +1230,16 @@ get_tex_coord(struct ir3_compile_context *ctx,
 
 		/* fix up .y coord: */
 		if (is_1d(tex)) {
+			struct ir3_register *imm;
 			instr = instr_create(ctx, 1, 0);  /* mov */
 			instr->cat1.src_type = type_mov;
 			instr->cat1.dst_type = type_mov;
 			add_dst_reg(ctx, instr, &tmp_dst, 1);  /* .y */
-			ir3_reg_create(instr, 0, IR3_REG_IMMED)->fim_val = 0.5;
+			imm = ir3_reg_create(instr, 0, IR3_REG_IMMED);
+			if (inst->Instruction.Opcode == TGSI_OPCODE_TXF)
+				imm->iim_val = 0;
+			else
+				imm->fim_val = 0.5;
 		}
 
 		coord = tmp_src;
@@ -2158,6 +2164,7 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = {
 	INSTR(TXB,          trans_samp, .opc = OPC_SAMB, .arg = TGSI_OPCODE_TXB),
 	INSTR(TXB2,         trans_samp, .opc = OPC_SAMB, .arg = TGSI_OPCODE_TXB2),
 	INSTR(TXL,          trans_samp, .opc = OPC_SAML, .arg = TGSI_OPCODE_TXL),
+	INSTR(TXF,          trans_samp, .opc = OPC_ISAML, .arg = TGSI_OPCODE_TXF),
 	INSTR(TXQ,          trans_txq),
 	INSTR(DDX,          trans_deriv, .opc = OPC_DSX),
 	INSTR(DDY,          trans_deriv, .opc = OPC_DSY),
-- 
1.8.5.5