[Freedreno] [PATCH] fixup! mdp5: Separate MDP5 domain from MDSS domain

[Stephane Viau]

Some bits added in "rnndb: Add registers needed by DSI in mdp5"
got somehow forgotten during the MDP5 domain separation..

This change fixes that up and makes sure SPLIT_DPL_EN/UPPER/LOWER
registers are at the right address for all chipsets.

Signed-off-by: Stephane Viau <sviau at codeaurora.org>
---
 rnndb/mdp/mdp5.xml | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index 03dcc3a..c52f92c 100644
--- a/rnndb/mdp/mdp5.xml
+++ b/rnndb/mdp/mdp5.xml
@@ -193,21 +193,21 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 				</reg32>
 			</array>
 		</array>
+		<reg32 offset="0x002f4" name="SPLIT_DPL_EN"/>
+		<reg32 offset="0x002f8" name="SPLIT_DPL_UPPER">
+			<bitfield name="SMART_PANEL" pos="1" type="boolean"/>
+			<bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
+			<bitfield name="INTF1_SW_TRG_MUX" pos="4" type="boolean"/>
+			<bitfield name="INTF2_SW_TRG_MUX" pos="8" type="boolean"/>
+		</reg32>
+		<reg32 offset="0x003f0" name="SPLIT_DPL_LOWER">
+			<bitfield name="SMART_PANEL" pos="1" type="boolean"/>
+			<bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
+			<bitfield name="INTF1_TG_SYNC" pos="4" type="boolean"/>
+			<bitfield name="INTF2_TG_SYNC" pos="8" type="boolean"/>
+		</reg32>
 	</array>
 
-	<reg32 offset="0x003f4" name="SPLIT_DPL_EN"/>
-	<reg32 offset="0x003f8" name="SPLIT_DPL_UPPER">
-		<bitfield name="SMART_PANEL" pos="1" type="boolean"/>
-		<bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
-		<bitfield name="INTF1_SW_TRG_MUX" pos="4" type="boolean"/>
-		<bitfield name="INTF2_SW_TRG_MUX" pos="8" type="boolean"/>
-	</reg32>
-	<reg32 offset="0x004f0" name="SPLIT_DPL_LOWER">
-		<bitfield name="SMART_PANEL" pos="1" type="boolean"/>
-		<bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
-		<bitfield name="INTF1_TG_SYNC" pos="4" type="boolean"/>
-		<bitfield name="INTF2_TG_SYNC" pos="8" type="boolean"/>
-	</reg32>
 <!-- check length/index.. -->
 	<array doffsets="mdp5_cfg->ctl.base[0],mdp5_cfg->ctl.base[1],mdp5_cfg->ctl.base[2],mdp5_cfg->ctl.base[3],mdp5_cfg->ctl.base[4]" name="CTL" length="5" stride="0x400">
 		<array offsets="0x000,0x004,0x008,0x00C,0x010,0x024" name="LAYER" length="6" stride="4">
-- 
Qualcomm Innovation Center, Inc.

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