[Freedreno] [PATCH] cffdump: add GS/HS/DS support, border color dumping

[Ilia Mirkin]

---
 includes/a4xx.xml.h       | 19 +++++++++++++++++++
 includes/adreno_pm4.xml.h |  1 +
 util/cffdump.c            | 12 ++++++++++++
 3 files changed, 32 insertions(+)

diff --git a/includes/a4xx.xml.h b/includes/a4xx.xml.h
index e9786ad..a100d54 100644
--- a/includes/a4xx.xml.h
+++ b/includes/a4xx.xml.h
@@ -741,8 +741,21 @@ static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
 
 #define REG_A4XX_SP_FS_PVT_MEM_ADDR				0x000022ed
 
+#define REG_A4XX_SP_GS_OBJ_START				0x0000235c
+#define REG_A4XX_SP_GS_PVT_MEM_PARAM				0x0000235d
+#define REG_A4XX_SP_GS_PVT_MEM_ADDR				0x0000235e
 #define REG_A4XX_SP_GS_LENGTH					0x00002360
 
+#define REG_A4XX_SP_HS_OBJ_START				0x0000230e
+#define REG_A4XX_SP_HS_PVT_MEM_PARAM				0x0000230f
+#define REG_A4XX_SP_HS_PVT_MEM_ADDR				0x00002310
+#define REG_A4XX_SP_HS_LENGTH					0x00002312
+
+#define REG_A4XX_SP_DS_OBJ_START				0x00002335
+#define REG_A4XX_SP_DS_PVT_MEM_PARAM				0x00002336
+#define REG_A4XX_SP_DS_PVT_MEM_ADDR				0x00002337
+#define REG_A4XX_SP_DS_LENGTH					0x00002339
+
 #define REG_A4XX_VPC_DEBUG_RAM_SEL				0x00000e60
 
 #define REG_A4XX_VPC_DEBUG_RAM_READ				0x00000e61
@@ -951,6 +964,12 @@ static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
 
 #define REG_A4XX_TPL1_TP_TEX_OFFSET				0x00002380
 
+#define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR		0x00002384
+#define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR		0x00002387
+#define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR		0x0000238a
+#define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR		0x0000238d
+#define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR		0x000023a1
+
 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR			0x000023a6
 
 #define REG_A4XX_GRAS_TSE_STATUS				0x00000c80
diff --git a/includes/adreno_pm4.xml.h b/includes/adreno_pm4.xml.h
index 522e74e..ab8db22 100644
--- a/includes/adreno_pm4.xml.h
+++ b/includes/adreno_pm4.xml.h
@@ -185,6 +185,7 @@ enum adreno_state_block {
 	SB_FRAG_TEX = 2,
 	SB_FRAG_MIPADDR = 3,
 	SB_VERT_SHADER = 4,
+	SB_GEOM_SHADER = 5,
 	SB_FRAG_SHADER = 6,
 };
 
diff --git a/util/cffdump.c b/util/cffdump.c
index 8fdd439..ce46dc1 100644
--- a/util/cffdump.c
+++ b/util/cffdump.c
@@ -609,8 +609,14 @@ static const const struct {
 #define REG(x, fxn) [REG_A4XX_ ## x] = { fxn }
 		REG(SP_VS_PVT_MEM_ADDR, reg_dump_gpuaddr),
 		REG(SP_FS_PVT_MEM_ADDR, reg_dump_gpuaddr),
+		REG(SP_GS_PVT_MEM_ADDR, reg_dump_gpuaddr),
+		REG(SP_HS_PVT_MEM_ADDR, reg_dump_gpuaddr),
+		REG(SP_DS_PVT_MEM_ADDR, reg_dump_gpuaddr),
 		REG(SP_VS_OBJ_START, reg_disasm_gpuaddr),
 		REG(SP_FS_OBJ_START, reg_disasm_gpuaddr),
+		REG(SP_GS_OBJ_START, reg_disasm_gpuaddr),
+		REG(SP_HS_OBJ_START, reg_disasm_gpuaddr),
+		REG(SP_DS_OBJ_START, reg_disasm_gpuaddr),
 		REG(VFD_FETCH_INSTR_0(0), reg_vfd_fetch_instr_0_x),
 		REG(VFD_FETCH_INSTR_1(0), reg_vfd_fetch_instr_1_x),
 		REG(VFD_FETCH_INSTR_0(1), reg_vfd_fetch_instr_0_x),
@@ -643,6 +649,11 @@ static const const struct {
 		REG(VFD_FETCH_INSTR_1(14), reg_vfd_fetch_instr_1_x),
 		REG(VFD_FETCH_INSTR_0(15), reg_vfd_fetch_instr_0_x),
 		REG(VFD_FETCH_INSTR_1(15), reg_vfd_fetch_instr_1_x),
+		REG(TPL1_TP_VS_BORDER_COLOR_BASE_ADDR, reg_dump_gpuaddr),
+		REG(TPL1_TP_HS_BORDER_COLOR_BASE_ADDR, reg_dump_gpuaddr),
+		REG(TPL1_TP_DS_BORDER_COLOR_BASE_ADDR, reg_dump_gpuaddr),
+		REG(TPL1_TP_GS_BORDER_COLOR_BASE_ADDR, reg_dump_gpuaddr),
+		REG(TPL1_TP_FS_BORDER_COLOR_BASE_ADDR, reg_dump_gpuaddr),
 #undef REG
 }, *type0_reg;
 
@@ -893,6 +904,7 @@ static void cp_load_state(uint32_t *dwords, uint32_t sizedwords, int level)
 
 	switch (state_block_id) {
 	case SB_FRAG_SHADER:
+	case SB_GEOM_SHADER:
 	case SB_VERT_SHADER:
 		if (state_type == ST_SHADER) {
 			enum shader_t disasm_type;
-- 
2.4.10