[Freedreno] [PATCH 1/2] arm64: dts: Use OPP table for Adreno GPU

[Jordan Crouse]

Add a nvmem cell to let the GPU driver read a speed bin from the
fuses (if applicable). Then switch the cpu frequency table definitions
to real OPP v2 tables so we can take advantage of the hardware matching
mechanism.

Signed-off-by: Jordan Crouse <jcrouse at codeaurora.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 34 ++++++++++++++++++++++------------
 1 file changed, 22 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 65fd370..f136d4c 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -642,6 +642,11 @@
 				reg = <0x24f 0x1>;
 				bits = <1 4>;
 			};
+
+			gpu_speed_bin: gpu_speed_bin at 133 {
+				reg = <0x133 0x1>;
+				bits = <5 3>;
+			};
 		};
 
 		phy at 34000 {
@@ -1099,6 +1104,19 @@
 			status = "okay";
 		};
 
+		gpu_opp_table: opp_table {
+			compatible  ="operating-points-v2";
+
+			opp-624000000 {
+				opp-hz = /bits/ 64 <624000000>;
+				opp-supported-hw = <0x01>;
+			};
+			opp-510000000 {
+				opp-hz = /bits/ 64 <510000000>;
+				opp-supported-hw = <0xFF>;
+			};
+		};
+
 		gpu at b00000 {
 			compatible = "qcom,adreno-530.2", "qcom,adreno";
 			#stream-id-cells = <16>;
@@ -1124,21 +1142,13 @@
 			power-domains = <&mmcc GPU_GDSC>;
 			iommus = <&adreno_smmu 0>;
 
+			nvmem-cells = <&gpu_speed_bin>;
+			nvmem-cell-names = "speed_bin";
+
 			qcom,gpu-quirk-two-pass-use-wfi;
 			qcom,gpu-quirk-fault-detect-mask;
 
-			/* This is a safe speed for bring up in all bin levels.
-			 * This isn't the fastest the chip can go, but we can
-			 * get there eventually */
-			qcom,gpu-pwrlevels {
-				compatible = "qcom,gpu-pwrlevels";
-				qcom,gpu-pwrlevel at 0 {
-					qcom,gpu-freq = <624000000>;
-				};
-				qcom,gpu-pwrlevel at 1 {
-					qcom,gpu-freq = <27000000>;
-				};
-			};
+			operating-points-v2 = <&gpu_opp_table>;
 
 			zap-shader {
 				memory-region = <&zap_shader_region>;
-- 
1.9.1