[Freedreno] [v7 PATCH 0/5] Add support for Adreno a6xx

[Jordan Crouse]

This is an initial version of support for the Adreno a6xx GPU family starting
with the a630 from the sdm845 SoC. This code is ahead of much of the sdm845
code that would be needed to actually bring up a device and it is also in
advance of any user side support for the a6xx GPU so this is mainly just a
chance to look over the code structure and get a feel for the
direction that the hardware is going in.

The a6xx GPU is an iteration of a5xx so most of the GPU side code looks pretty
identical except for the usual register differences. The big different is in
power control. On the a5xx there was a rudimentary device called the GPMU that
did some basic power stuff but left most of the complexity to the kernel.

On the a6xx the power complexity is being moved to a component
called the GMU (graphics management unit) which handles the power control of the
GPU and shuts it down quickly after it goes idle.

This stack has one run time dependency that shifts the power responsibility
for the SMMU to the SMMU driver instead of the current workaround of implicitly
powering the SMMU by powering the GPU:

https://patchwork.kernel.org/patch/10301163/ - pm_runtime ops for arm-smmu

[v7 - Make sure the GMU sets the GPU clock to something reasonable. Force the
GPU/GMU on during state capture to avoid errors.  Fix checkpatch errors]

[v6 - set nr_clocks to 0 when parsing fails and minor cleanup in msm_iommu for
Vivek. Fix compile error in the load firmware patch ]

[v5 - Move firmware loading to adreno_load_gpu() so it is easier to fail if the
firmware isn't found ]

[v4 - Add clock parsing helper function and use it for GPU and GMU. Update
recommended clock gating settings. Fix a bug in the CMD DB parser. Update
register values from updated database ]

[v3 - fix inverted register definition for GMU_SPTPRAC_CLK_STATUS; fix incorrect
register check in a5xx_gmu_gx_is_on(), use dev_pm_opp_get_of_node() from
Rajendra and Viresh to read the qcom,level from the device tree; read qcom,level
from the DT to get the voltage level to pass to the GMU, fix issues
identified by smatch]

[v2 - addressed comments from Lucas Stach; added pm_runtime_get_supplier calls
for accesses to the GMU IOMMU; moved to SPDX headers for new files]

Jordan Crouse (4):
  drm/msm: Remove pm_runtime operations from msm_iommu
  drm/msm: Add a helper function to parse clock names
  drm/msm/adreno: Load the firmware before bringing up the hardware
  drm/msm: Add A6XX device support

Sharat Masetty (1):
  drm/msm: Add generated headers for A6XX

 drivers/gpu/drm/msm/Makefile               |    3 +
 drivers/gpu/drm/msm/adreno/a6xx.xml.h      | 1784 ++++++++++++++++++++
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c      | 1207 +++++++++++++
 drivers/gpu/drm/msm/adreno/a6xx_gmu.h      |  162 ++
 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h  |  382 +++++
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c      |  818 +++++++++
 drivers/gpu/drm/msm/adreno/a6xx_gpu.h      |   60 +
 drivers/gpu/drm/msm/adreno/a6xx_hfi.c      |  435 +++++
 drivers/gpu/drm/msm/adreno/a6xx_hfi.h      |  127 ++
 drivers/gpu/drm/msm/adreno/adreno_device.c |   35 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.c    |    2 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h    |    5 +-
 drivers/gpu/drm/msm/msm_drv.c              |   57 +
 drivers/gpu/drm/msm/msm_drv.h              |    4 +
 drivers/gpu/drm/msm/msm_gpu.c              |   62 +-
 drivers/gpu/drm/msm/msm_gpu.h              |    2 +-
 drivers/gpu/drm/msm/msm_iommu.c            |   13 +-
 17 files changed, 5091 insertions(+), 67 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx.xml.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.c
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gpu.c
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_gpu.h
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_hfi.c
 create mode 100644 drivers/gpu/drm/msm/adreno/a6xx_hfi.h

-- 
2.18.0