[Freedreno] [PATCH] rnndb: a6xx: Add kernel registers for the GPU and GMU
Jordan Crouse
jcrouse at codeaurora.org
Wed Jan 31 18:06:45 UTC 2018
Add the kernel side registers needed to bring up and use the
a6xx GPU and GMU to the rnndb database.
---
rnndb/adreno.xml | 2 +
rnndb/adreno/a6xx.xml | 830 ++++++++++++++++++++++++++++++++++++++++++++++
rnndb/adreno/a6xx_gmu.xml | 211 ++++++++++++
3 files changed, 1043 insertions(+)
create mode 100644 rnndb/adreno/a6xx.xml
create mode 100644 rnndb/adreno/a6xx_gmu.xml
diff --git a/rnndb/adreno.xml b/rnndb/adreno.xml
index eebd087..0dbf829 100644
--- a/rnndb/adreno.xml
+++ b/rnndb/adreno.xml
@@ -8,6 +8,8 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<import file="adreno/a3xx.xml"/>
<import file="adreno/a4xx.xml"/>
<import file="adreno/a5xx.xml"/>
+<import file="adreno/a6xx.xml"/>
+<import file="adreno/a6xx_gmu.xml"/>
<import file="adreno/ocmem.xml"/>
</database>
diff --git a/rnndb/adreno/a6xx.xml b/rnndb/adreno/a6xx.xml
new file mode 100644
index 0000000..b74c7d2
--- /dev/null
+++ b/rnndb/adreno/a6xx.xml
@@ -0,0 +1,830 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
+<import file="freedreno_copyright.xml"/>
+<import file="adreno/adreno_common.xml"/>
+<import file="adreno/adreno_pm4.xml"/>
+
+<bitset name="a6x_cp_protect" inline="yes">
+ <bitfield name="BASE_ADDR" low="0" high="17"/>
+ <bitfield name="MASK_LEN" low="18" high="30"/>
+ <bitfield name="READ" pos="31"/>
+</bitset>
+
+<enum name="a6xx_cp_perfcounter_select">
+ <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
+</enum>
+
+<enum name="a6xx_event_write">
+ <value value="24" name="PC_CCU_INVALIDATE_DEPTH"/>
+ <value value="25" name="PC_CCU_INVALIDATE_COLOR"/>
+</enum>
+
+<domain name="A6XX" width="32">
+ <bitset name="A6XX_RBBM_INT_0_MASK">
+ <bitfield name="RBBM_GPU_IDLE" pos="0"/>
+ <bitfield name="CP_AHB_ERROR" pos="1"/>
+ <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6"/>
+ <bitfield name="RBBM_GPC_ERROR" pos="7"/>
+ <bitfield name="CP_SW" pos="8"/>
+ <bitfield name="CP_HW_ERROR" pos="9"/>
+ <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/>
+ <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/>
+ <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/>
+ <bitfield name="CP_IB2" pos="13"/>
+ <bitfield name="CP_IB1" pos="14"/>
+ <bitfield name="CP_RB" pos="15"/>
+ <bitfield name="CP_RB_DONE_TS" pos="17"/>
+ <bitfield name="CP_WT_DONE_TS" pos="18"/>
+ <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/>
+ <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/>
+ <bitfield name="RBBM_HANG_DETECT" pos="23"/>
+ <bitfield name="UCHE_OOB_ACCESS" pos="24"/>
+ <bitfield name="UCHE_TRAP_INTR" pos="25"/>
+ <bitfield name="DEBBUS_INTR_0" pos="26"/>
+ <bitfield name="DEBBUS_INTR_1" pos="27"/>
+ <bitfield name="ISDB_CPU_IRQ" pos="30"/>
+ <bitfield name="ISDB_UNDER_DEBUG" pos="31"/>
+ </bitset>
+
+ <bitset name="A6XX_CP_INT">
+ <bitfield name="CP_OPCODE_ERROR" pos="0"/>
+ <bitfield name="CP_UCODE_ERROR" pos="1"/>
+ <bitfield name="CP_HW_FAULT_ERROR" pos="2"/>
+ <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/>
+ <bitfield name="CP_AHB_ERROR" pos="5"/>
+ <bitfield name="CP_VSD_PARITY_ERROR" pos="6"/>
+ <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7"/>
+ </bitset>
+
+ <reg32 offset="0x0800" name="CP_RB_BASE"/>
+ <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
+ <reg32 offset="0x0802" name="CP_RB_CNTL"/>
+ <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
+ <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
+ <reg32 offset="0x0806" name="CP_RB_RPTR"/>
+ <reg32 offset="0x0807" name="CP_RB_WPTR"/>
+ <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
+ <reg32 offset="0x0821" name="CP_HW_FAULT"/>
+ <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
+ <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
+ <reg32 offset="0x0830" name="CP_SQE_INSTR_BASE_LO"/>
+ <reg32 offset="0x0831" name="CP_SQE_INSTR_BASE_HI"/>
+ <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
+ <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1"/>
+ <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2"/>
+ <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
+ <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
+ <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL"/>
+ <reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>
+
+ <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
+ <reg32 offset="0x0" name="REG" type="uint"/>
+ </array>
+ <array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
+ <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
+ </array>
+
+ <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
+ <reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
+ <reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
+ <reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/>
+ <reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/>
+ <reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/>
+ <reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
+ <reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
+ <reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
+ <reg32 offset="0x08D0" name="CP_PERFCTR_CP_SEL_0"/>
+ <reg32 offset="0x08D1" name="CP_PERFCTR_CP_SEL_1"/>
+ <reg32 offset="0x08D2" name="CP_PERFCTR_CP_SEL_2"/>
+ <reg32 offset="0x08D3" name="CP_PERFCTR_CP_SEL_3"/>
+ <reg32 offset="0x08D4" name="CP_PERFCTR_CP_SEL_4"/>
+ <reg32 offset="0x08D5" name="CP_PERFCTR_CP_SEL_5"/>
+ <reg32 offset="0x08D6" name="CP_PERFCTR_CP_SEL_6"/>
+ <reg32 offset="0x08D7" name="CP_PERFCTR_CP_SEL_7"/>
+ <reg32 offset="0x08D8" name="CP_PERFCTR_CP_SEL_8"/>
+ <reg32 offset="0x08D9" name="CP_PERFCTR_CP_SEL_9"/>
+ <reg32 offset="0x08DA" name="CP_PERFCTR_CP_SEL_10"/>
+ <reg32 offset="0x08DB" name="CP_PERFCTR_CP_SEL_11"/>
+ <reg32 offset="0x08DC" name="CP_PERFCTR_CP_SEL_12"/>
+ <reg32 offset="0x08DD" name="CP_PERFCTR_CP_SEL_13"/>
+ <reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
+ <reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
+ <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
+ <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
+ <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
+ <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
+ <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
+ <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
+ <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
+ <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
+ <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
+ <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
+ <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
+ <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
+ <reg32 offset="0x0928" name="CP_IB1_BASE"/>
+ <reg32 offset="0x0929" name="CP_IB1_BASE_HI"/>
+ <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
+ <reg32 offset="0x092B" name="CP_IB2_BASE"/>
+ <reg32 offset="0x092C" name="CP_IB2_BASE_HI"/>
+ <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
+ <reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
+ <reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
+ <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
+ <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
+ <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL"/>
+ <reg32 offset="0x0201" name="RBBM_INT_0_STATUS"/>
+ <reg32 offset="0x0210" name="RBBM_STATUS">
+ <bitfield high="23" low="23" name="GPU_BUSY_IGN_AHB" />
+ <bitfield high="22" low="22" name="GPU_BUSY_IGN_AHB_CP" />
+ <bitfield high="21" low="21" name="HLSQ_BUSY" />
+ <bitfield high="20" low="20" name="VSC_BUSY" />
+ <bitfield high="19" low="19" name="TPL1_BUSY" />
+ <bitfield high="18" low="18" name="SP_BUSY" />
+ <bitfield high="17" low="17" name="UCHE_BUSY" />
+ <bitfield high="16" low="16" name="VPC_BUSY" />
+ <bitfield high="15" low="15" name="VFD_BUSY" />
+ <bitfield high="14" low="14" name="TESS_BUSY" />
+ <bitfield high="13" low="13" name="PC_VSD_BUSY" />
+ <bitfield high="12" low="12" name="PC_DCALL_BUSY" />
+ <bitfield high="11" low="11" name="COM_DCOM_BUSY" />
+ <bitfield high="10" low="10" name="LRZ_BUSY" />
+ <bitfield high="9" low="9" name="A2D_BUSY" />
+ <bitfield high="8" low="8" name="CCU_BUSY" />
+ <bitfield high="7" low="7" name="RB_BUSY" />
+ <bitfield high="6" low="6" name="RAS_BUSY" />
+ <bitfield high="5" low="5" name="TSE_BUSY" />
+ <bitfield high="4" low="4" name="VBIF_BUSY" />
+ <bitfield high="3" low="3" name="GFX_DBGC_BUSY" />
+ <bitfield high="2" low="2" name="CP_BUSY" />
+ <bitfield high="1" low="1" name="CP_AHB_BUSY_CP_MASTER" />
+ <bitfield high="0" low="0" name="CP_AHB_BUSY_CX_MASTER"/>
+ </reg32>
+ <reg32 offset="0x0213" name="RBBM_STATUS3"/>
+ <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
+ <reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
+ <reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>
+ <reg32 offset="0x0402" name="RBBM_PERFCTR_CP_1_LO"/>
+ <reg32 offset="0x0403" name="RBBM_PERFCTR_CP_1_HI"/>
+ <reg32 offset="0x0404" name="RBBM_PERFCTR_CP_2_LO"/>
+ <reg32 offset="0x0405" name="RBBM_PERFCTR_CP_2_HI"/>
+ <reg32 offset="0x0406" name="RBBM_PERFCTR_CP_3_LO"/>
+ <reg32 offset="0x0407" name="RBBM_PERFCTR_CP_3_HI"/>
+ <reg32 offset="0x0408" name="RBBM_PERFCTR_CP_4_LO"/>
+ <reg32 offset="0x0409" name="RBBM_PERFCTR_CP_4_HI"/>
+ <reg32 offset="0x040a" name="RBBM_PERFCTR_CP_5_LO"/>
+ <reg32 offset="0x040b" name="RBBM_PERFCTR_CP_5_HI"/>
+ <reg32 offset="0x040c" name="RBBM_PERFCTR_CP_6_LO"/>
+ <reg32 offset="0x040d" name="RBBM_PERFCTR_CP_6_HI"/>
+ <reg32 offset="0x040e" name="RBBM_PERFCTR_CP_7_LO"/>
+ <reg32 offset="0x040f" name="RBBM_PERFCTR_CP_7_HI"/>
+ <reg32 offset="0x0410" name="RBBM_PERFCTR_CP_8_LO"/>
+ <reg32 offset="0x0411" name="RBBM_PERFCTR_CP_8_HI"/>
+ <reg32 offset="0x0412" name="RBBM_PERFCTR_CP_9_LO"/>
+ <reg32 offset="0x0413" name="RBBM_PERFCTR_CP_9_HI"/>
+ <reg32 offset="0x0414" name="RBBM_PERFCTR_CP_10_LO"/>
+ <reg32 offset="0x0415" name="RBBM_PERFCTR_CP_10_HI"/>
+ <reg32 offset="0x0416" name="RBBM_PERFCTR_CP_11_LO"/>
+ <reg32 offset="0x0417" name="RBBM_PERFCTR_CP_11_HI"/>
+ <reg32 offset="0x0418" name="RBBM_PERFCTR_CP_12_LO"/>
+ <reg32 offset="0x0419" name="RBBM_PERFCTR_CP_12_HI"/>
+ <reg32 offset="0x041a" name="RBBM_PERFCTR_CP_13_LO"/>
+ <reg32 offset="0x041b" name="RBBM_PERFCTR_CP_13_HI"/>
+ <reg32 offset="0x041c" name="RBBM_PERFCTR_RBBM_0_LO"/>
+ <reg32 offset="0x041d" name="RBBM_PERFCTR_RBBM_0_HI"/>
+ <reg32 offset="0x041e" name="RBBM_PERFCTR_RBBM_1_LO"/>
+ <reg32 offset="0x041f" name="RBBM_PERFCTR_RBBM_1_HI"/>
+ <reg32 offset="0x0420" name="RBBM_PERFCTR_RBBM_2_LO"/>
+ <reg32 offset="0x0421" name="RBBM_PERFCTR_RBBM_2_HI"/>
+ <reg32 offset="0x0422" name="RBBM_PERFCTR_RBBM_3_LO"/>
+ <reg32 offset="0x0423" name="RBBM_PERFCTR_RBBM_3_HI"/>
+ <reg32 offset="0x0424" name="RBBM_PERFCTR_PC_0_LO"/>
+ <reg32 offset="0x0425" name="RBBM_PERFCTR_PC_0_HI"/>
+ <reg32 offset="0x0426" name="RBBM_PERFCTR_PC_1_LO"/>
+ <reg32 offset="0x0427" name="RBBM_PERFCTR_PC_1_HI"/>
+ <reg32 offset="0x0428" name="RBBM_PERFCTR_PC_2_LO"/>
+ <reg32 offset="0x0429" name="RBBM_PERFCTR_PC_2_HI"/>
+ <reg32 offset="0x042a" name="RBBM_PERFCTR_PC_3_LO"/>
+ <reg32 offset="0x042b" name="RBBM_PERFCTR_PC_3_HI"/>
+ <reg32 offset="0x042c" name="RBBM_PERFCTR_PC_4_LO"/>
+ <reg32 offset="0x042d" name="RBBM_PERFCTR_PC_4_HI"/>
+ <reg32 offset="0x042e" name="RBBM_PERFCTR_PC_5_LO"/>
+ <reg32 offset="0x042f" name="RBBM_PERFCTR_PC_5_HI"/>
+ <reg32 offset="0x0430" name="RBBM_PERFCTR_PC_6_LO"/>
+ <reg32 offset="0x0431" name="RBBM_PERFCTR_PC_6_HI"/>
+ <reg32 offset="0x0432" name="RBBM_PERFCTR_PC_7_LO"/>
+ <reg32 offset="0x0433" name="RBBM_PERFCTR_PC_7_HI"/>
+ <reg32 offset="0x0434" name="RBBM_PERFCTR_VFD_0_LO"/>
+ <reg32 offset="0x0435" name="RBBM_PERFCTR_VFD_0_HI"/>
+ <reg32 offset="0x0436" name="RBBM_PERFCTR_VFD_1_LO"/>
+ <reg32 offset="0x0437" name="RBBM_PERFCTR_VFD_1_HI"/>
+ <reg32 offset="0x0438" name="RBBM_PERFCTR_VFD_2_LO"/>
+ <reg32 offset="0x0439" name="RBBM_PERFCTR_VFD_2_HI"/>
+ <reg32 offset="0x043a" name="RBBM_PERFCTR_VFD_3_LO"/>
+ <reg32 offset="0x043b" name="RBBM_PERFCTR_VFD_3_HI"/>
+ <reg32 offset="0x043c" name="RBBM_PERFCTR_VFD_4_LO"/>
+ <reg32 offset="0x043d" name="RBBM_PERFCTR_VFD_4_HI"/>
+ <reg32 offset="0x043e" name="RBBM_PERFCTR_VFD_5_LO"/>
+ <reg32 offset="0x043f" name="RBBM_PERFCTR_VFD_5_HI"/>
+ <reg32 offset="0x0440" name="RBBM_PERFCTR_VFD_6_LO"/>
+ <reg32 offset="0x0441" name="RBBM_PERFCTR_VFD_6_HI"/>
+ <reg32 offset="0x0442" name="RBBM_PERFCTR_VFD_7_LO"/>
+ <reg32 offset="0x0443" name="RBBM_PERFCTR_VFD_7_HI"/>
+ <reg32 offset="0x0444" name="RBBM_PERFCTR_HLSQ_0_LO"/>
+ <reg32 offset="0x0445" name="RBBM_PERFCTR_HLSQ_0_HI"/>
+ <reg32 offset="0x0446" name="RBBM_PERFCTR_HLSQ_1_LO"/>
+ <reg32 offset="0x0447" name="RBBM_PERFCTR_HLSQ_1_HI"/>
+ <reg32 offset="0x0448" name="RBBM_PERFCTR_HLSQ_2_LO"/>
+ <reg32 offset="0x0449" name="RBBM_PERFCTR_HLSQ_2_HI"/>
+ <reg32 offset="0x044a" name="RBBM_PERFCTR_HLSQ_3_LO"/>
+ <reg32 offset="0x044b" name="RBBM_PERFCTR_HLSQ_3_HI"/>
+ <reg32 offset="0x044c" name="RBBM_PERFCTR_HLSQ_4_LO"/>
+ <reg32 offset="0x044d" name="RBBM_PERFCTR_HLSQ_4_HI"/>
+ <reg32 offset="0x044e" name="RBBM_PERFCTR_HLSQ_5_LO"/>
+ <reg32 offset="0x044f" name="RBBM_PERFCTR_HLSQ_5_HI"/>
+ <reg32 offset="0x0450" name="RBBM_PERFCTR_VPC_0_LO"/>
+ <reg32 offset="0x0451" name="RBBM_PERFCTR_VPC_0_HI"/>
+ <reg32 offset="0x0452" name="RBBM_PERFCTR_VPC_1_LO"/>
+ <reg32 offset="0x0453" name="RBBM_PERFCTR_VPC_1_HI"/>
+ <reg32 offset="0x0454" name="RBBM_PERFCTR_VPC_2_LO"/>
+ <reg32 offset="0x0455" name="RBBM_PERFCTR_VPC_2_HI"/>
+ <reg32 offset="0x0456" name="RBBM_PERFCTR_VPC_3_LO"/>
+ <reg32 offset="0x0457" name="RBBM_PERFCTR_VPC_3_HI"/>
+ <reg32 offset="0x0458" name="RBBM_PERFCTR_VPC_4_LO"/>
+ <reg32 offset="0x0459" name="RBBM_PERFCTR_VPC_4_HI"/>
+ <reg32 offset="0x045a" name="RBBM_PERFCTR_VPC_5_LO"/>
+ <reg32 offset="0x045b" name="RBBM_PERFCTR_VPC_5_HI"/>
+ <reg32 offset="0x045c" name="RBBM_PERFCTR_CCU_0_LO"/>
+ <reg32 offset="0x045d" name="RBBM_PERFCTR_CCU_0_HI"/>
+ <reg32 offset="0x045e" name="RBBM_PERFCTR_CCU_1_LO"/>
+ <reg32 offset="0x045f" name="RBBM_PERFCTR_CCU_1_HI"/>
+ <reg32 offset="0x0460" name="RBBM_PERFCTR_CCU_2_LO"/>
+ <reg32 offset="0x0461" name="RBBM_PERFCTR_CCU_2_HI"/>
+ <reg32 offset="0x0462" name="RBBM_PERFCTR_CCU_3_LO"/>
+ <reg32 offset="0x0463" name="RBBM_PERFCTR_CCU_3_HI"/>
+ <reg32 offset="0x0464" name="RBBM_PERFCTR_CCU_4_LO"/>
+ <reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/>
+ <reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/>
+ <reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/>
+ <reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/>
+ <reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/>
+ <reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/>
+ <reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/>
+ <reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/>
+ <reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/>
+ <reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/>
+ <reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/>
+ <reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/>
+ <reg32 offset="0x046b" name="RBBM_PERFCTR_TSE_2_HI"/>
+ <reg32 offset="0x046c" name="RBBM_PERFCTR_TSE_3_LO"/>
+ <reg32 offset="0x046d" name="RBBM_PERFCTR_TSE_3_HI"/>
+ <reg32 offset="0x046e" name="RBBM_PERFCTR_RAS_0_LO"/>
+ <reg32 offset="0x046f" name="RBBM_PERFCTR_RAS_0_HI"/>
+ <reg32 offset="0x0470" name="RBBM_PERFCTR_RAS_1_LO"/>
+ <reg32 offset="0x0471" name="RBBM_PERFCTR_RAS_1_HI"/>
+ <reg32 offset="0x0472" name="RBBM_PERFCTR_RAS_2_LO"/>
+ <reg32 offset="0x0473" name="RBBM_PERFCTR_RAS_2_HI"/>
+ <reg32 offset="0x0474" name="RBBM_PERFCTR_RAS_3_LO"/>
+ <reg32 offset="0x0475" name="RBBM_PERFCTR_RAS_3_HI"/>
+ <reg32 offset="0x0476" name="RBBM_PERFCTR_UCHE_0_LO"/>
+ <reg32 offset="0x0477" name="RBBM_PERFCTR_UCHE_0_HI"/>
+ <reg32 offset="0x0478" name="RBBM_PERFCTR_UCHE_1_LO"/>
+ <reg32 offset="0x0479" name="RBBM_PERFCTR_UCHE_1_HI"/>
+ <reg32 offset="0x047a" name="RBBM_PERFCTR_UCHE_2_LO"/>
+ <reg32 offset="0x047b" name="RBBM_PERFCTR_UCHE_2_HI"/>
+ <reg32 offset="0x047c" name="RBBM_PERFCTR_UCHE_3_LO"/>
+ <reg32 offset="0x047d" name="RBBM_PERFCTR_UCHE_3_HI"/>
+ <reg32 offset="0x047e" name="RBBM_PERFCTR_UCHE_4_LO"/>
+ <reg32 offset="0x047f" name="RBBM_PERFCTR_UCHE_4_HI"/>
+ <reg32 offset="0x0480" name="RBBM_PERFCTR_UCHE_5_LO"/>
+ <reg32 offset="0x0481" name="RBBM_PERFCTR_UCHE_5_HI"/>
+ <reg32 offset="0x0482" name="RBBM_PERFCTR_UCHE_6_LO"/>
+ <reg32 offset="0x0483" name="RBBM_PERFCTR_UCHE_6_HI"/>
+ <reg32 offset="0x0484" name="RBBM_PERFCTR_UCHE_7_LO"/>
+ <reg32 offset="0x0485" name="RBBM_PERFCTR_UCHE_7_HI"/>
+ <reg32 offset="0x0486" name="RBBM_PERFCTR_UCHE_8_LO"/>
+ <reg32 offset="0x0487" name="RBBM_PERFCTR_UCHE_8_HI"/>
+ <reg32 offset="0x0488" name="RBBM_PERFCTR_UCHE_9_LO"/>
+ <reg32 offset="0x0489" name="RBBM_PERFCTR_UCHE_9_HI"/>
+ <reg32 offset="0x048a" name="RBBM_PERFCTR_UCHE_10_LO"/>
+ <reg32 offset="0x048b" name="RBBM_PERFCTR_UCHE_10_HI"/>
+ <reg32 offset="0x048c" name="RBBM_PERFCTR_UCHE_11_LO"/>
+ <reg32 offset="0x048d" name="RBBM_PERFCTR_UCHE_11_HI"/>
+ <reg32 offset="0x048e" name="RBBM_PERFCTR_TP_0_LO"/>
+ <reg32 offset="0x048f" name="RBBM_PERFCTR_TP_0_HI"/>
+ <reg32 offset="0x0490" name="RBBM_PERFCTR_TP_1_LO"/>
+ <reg32 offset="0x0491" name="RBBM_PERFCTR_TP_1_HI"/>
+ <reg32 offset="0x0492" name="RBBM_PERFCTR_TP_2_LO"/>
+ <reg32 offset="0x0493" name="RBBM_PERFCTR_TP_2_HI"/>
+ <reg32 offset="0x0494" name="RBBM_PERFCTR_TP_3_LO"/>
+ <reg32 offset="0x0495" name="RBBM_PERFCTR_TP_3_HI"/>
+ <reg32 offset="0x0496" name="RBBM_PERFCTR_TP_4_LO"/>
+ <reg32 offset="0x0497" name="RBBM_PERFCTR_TP_4_HI"/>
+ <reg32 offset="0x0498" name="RBBM_PERFCTR_TP_5_LO"/>
+ <reg32 offset="0x0499" name="RBBM_PERFCTR_TP_5_HI"/>
+ <reg32 offset="0x049a" name="RBBM_PERFCTR_TP_6_LO"/>
+ <reg32 offset="0x049b" name="RBBM_PERFCTR_TP_6_HI"/>
+ <reg32 offset="0x049c" name="RBBM_PERFCTR_TP_7_LO"/>
+ <reg32 offset="0x049d" name="RBBM_PERFCTR_TP_7_HI"/>
+ <reg32 offset="0x049e" name="RBBM_PERFCTR_TP_8_LO"/>
+ <reg32 offset="0x049f" name="RBBM_PERFCTR_TP_8_HI"/>
+ <reg32 offset="0x04a0" name="RBBM_PERFCTR_TP_9_LO"/>
+ <reg32 offset="0x04a1" name="RBBM_PERFCTR_TP_9_HI"/>
+ <reg32 offset="0x04a2" name="RBBM_PERFCTR_TP_10_LO"/>
+ <reg32 offset="0x04a3" name="RBBM_PERFCTR_TP_10_HI"/>
+ <reg32 offset="0x04a4" name="RBBM_PERFCTR_TP_11_LO"/>
+ <reg32 offset="0x04a5" name="RBBM_PERFCTR_TP_11_HI"/>
+ <reg32 offset="0x04a6" name="RBBM_PERFCTR_SP_0_LO"/>
+ <reg32 offset="0x04a7" name="RBBM_PERFCTR_SP_0_HI"/>
+ <reg32 offset="0x04a8" name="RBBM_PERFCTR_SP_1_LO"/>
+ <reg32 offset="0x04a9" name="RBBM_PERFCTR_SP_1_HI"/>
+ <reg32 offset="0x04aa" name="RBBM_PERFCTR_SP_2_LO"/>
+ <reg32 offset="0x04ab" name="RBBM_PERFCTR_SP_2_HI"/>
+ <reg32 offset="0x04ac" name="RBBM_PERFCTR_SP_3_LO"/>
+ <reg32 offset="0x04ad" name="RBBM_PERFCTR_SP_3_HI"/>
+ <reg32 offset="0x04ae" name="RBBM_PERFCTR_SP_4_LO"/>
+ <reg32 offset="0x04af" name="RBBM_PERFCTR_SP_4_HI"/>
+ <reg32 offset="0x04b0" name="RBBM_PERFCTR_SP_5_LO"/>
+ <reg32 offset="0x04b1" name="RBBM_PERFCTR_SP_5_HI"/>
+ <reg32 offset="0x04b2" name="RBBM_PERFCTR_SP_6_LO"/>
+ <reg32 offset="0x04b3" name="RBBM_PERFCTR_SP_6_HI"/>
+ <reg32 offset="0x04b4" name="RBBM_PERFCTR_SP_7_LO"/>
+ <reg32 offset="0x04b5" name="RBBM_PERFCTR_SP_7_HI"/>
+ <reg32 offset="0x04b6" name="RBBM_PERFCTR_SP_8_LO"/>
+ <reg32 offset="0x04b7" name="RBBM_PERFCTR_SP_8_HI"/>
+ <reg32 offset="0x04b8" name="RBBM_PERFCTR_SP_9_LO"/>
+ <reg32 offset="0x04b9" name="RBBM_PERFCTR_SP_9_HI"/>
+ <reg32 offset="0x04ba" name="RBBM_PERFCTR_SP_10_LO"/>
+ <reg32 offset="0x04bb" name="RBBM_PERFCTR_SP_10_HI"/>
+ <reg32 offset="0x04bc" name="RBBM_PERFCTR_SP_11_LO"/>
+ <reg32 offset="0x04bd" name="RBBM_PERFCTR_SP_11_HI"/>
+ <reg32 offset="0x04be" name="RBBM_PERFCTR_SP_12_LO"/>
+ <reg32 offset="0x04bf" name="RBBM_PERFCTR_SP_12_HI"/>
+ <reg32 offset="0x04c0" name="RBBM_PERFCTR_SP_13_LO"/>
+ <reg32 offset="0x04c1" name="RBBM_PERFCTR_SP_13_HI"/>
+ <reg32 offset="0x04c2" name="RBBM_PERFCTR_SP_14_LO"/>
+ <reg32 offset="0x04c3" name="RBBM_PERFCTR_SP_14_HI"/>
+ <reg32 offset="0x04c4" name="RBBM_PERFCTR_SP_15_LO"/>
+ <reg32 offset="0x04c5" name="RBBM_PERFCTR_SP_15_HI"/>
+ <reg32 offset="0x04c6" name="RBBM_PERFCTR_SP_16_LO"/>
+ <reg32 offset="0x04c7" name="RBBM_PERFCTR_SP_16_HI"/>
+ <reg32 offset="0x04c8" name="RBBM_PERFCTR_SP_17_LO"/>
+ <reg32 offset="0x04c9" name="RBBM_PERFCTR_SP_17_HI"/>
+ <reg32 offset="0x04ca" name="RBBM_PERFCTR_SP_18_LO"/>
+ <reg32 offset="0x04cb" name="RBBM_PERFCTR_SP_18_HI"/>
+ <reg32 offset="0x04cc" name="RBBM_PERFCTR_SP_19_LO"/>
+ <reg32 offset="0x04cd" name="RBBM_PERFCTR_SP_19_HI"/>
+ <reg32 offset="0x04ce" name="RBBM_PERFCTR_SP_20_LO"/>
+ <reg32 offset="0x04cf" name="RBBM_PERFCTR_SP_20_HI"/>
+ <reg32 offset="0x04d0" name="RBBM_PERFCTR_SP_21_LO"/>
+ <reg32 offset="0x04d1" name="RBBM_PERFCTR_SP_21_HI"/>
+ <reg32 offset="0x04d2" name="RBBM_PERFCTR_SP_22_LO"/>
+ <reg32 offset="0x04d3" name="RBBM_PERFCTR_SP_22_HI"/>
+ <reg32 offset="0x04d4" name="RBBM_PERFCTR_SP_23_LO"/>
+ <reg32 offset="0x04d5" name="RBBM_PERFCTR_SP_23_HI"/>
+ <reg32 offset="0x04d6" name="RBBM_PERFCTR_RB_0_LO"/>
+ <reg32 offset="0x04d7" name="RBBM_PERFCTR_RB_0_HI"/>
+ <reg32 offset="0x04d8" name="RBBM_PERFCTR_RB_1_LO"/>
+ <reg32 offset="0x04d9" name="RBBM_PERFCTR_RB_1_HI"/>
+ <reg32 offset="0x04da" name="RBBM_PERFCTR_RB_2_LO"/>
+ <reg32 offset="0x04db" name="RBBM_PERFCTR_RB_2_HI"/>
+ <reg32 offset="0x04dc" name="RBBM_PERFCTR_RB_3_LO"/>
+ <reg32 offset="0x04dd" name="RBBM_PERFCTR_RB_3_HI"/>
+ <reg32 offset="0x04de" name="RBBM_PERFCTR_RB_4_LO"/>
+ <reg32 offset="0x04df" name="RBBM_PERFCTR_RB_4_HI"/>
+ <reg32 offset="0x04e0" name="RBBM_PERFCTR_RB_5_LO"/>
+ <reg32 offset="0x04e1" name="RBBM_PERFCTR_RB_5_HI"/>
+ <reg32 offset="0x04e2" name="RBBM_PERFCTR_RB_6_LO"/>
+ <reg32 offset="0x04e3" name="RBBM_PERFCTR_RB_6_HI"/>
+ <reg32 offset="0x04e4" name="RBBM_PERFCTR_RB_7_LO"/>
+ <reg32 offset="0x04e5" name="RBBM_PERFCTR_RB_7_HI"/>
+ <reg32 offset="0x04e6" name="RBBM_PERFCTR_VSC_0_LO"/>
+ <reg32 offset="0x04e7" name="RBBM_PERFCTR_VSC_0_HI"/>
+ <reg32 offset="0x04e8" name="RBBM_PERFCTR_VSC_1_LO"/>
+ <reg32 offset="0x04e9" name="RBBM_PERFCTR_VSC_1_HI"/>
+ <reg32 offset="0x04ea" name="RBBM_PERFCTR_LRZ_0_LO"/>
+ <reg32 offset="0x04eb" name="RBBM_PERFCTR_LRZ_0_HI"/>
+ <reg32 offset="0x04ec" name="RBBM_PERFCTR_LRZ_1_LO"/>
+ <reg32 offset="0x04ed" name="RBBM_PERFCTR_LRZ_1_HI"/>
+ <reg32 offset="0x04ee" name="RBBM_PERFCTR_LRZ_2_LO"/>
+ <reg32 offset="0x04ef" name="RBBM_PERFCTR_LRZ_2_HI"/>
+ <reg32 offset="0x04f0" name="RBBM_PERFCTR_LRZ_3_LO"/>
+ <reg32 offset="0x04f1" name="RBBM_PERFCTR_LRZ_3_HI"/>
+ <reg32 offset="0x04f2" name="RBBM_PERFCTR_CMP_0_LO"/>
+ <reg32 offset="0x04f3" name="RBBM_PERFCTR_CMP_0_HI"/>
+ <reg32 offset="0x04f4" name="RBBM_PERFCTR_CMP_1_LO"/>
+ <reg32 offset="0x04f5" name="RBBM_PERFCTR_CMP_1_HI"/>
+ <reg32 offset="0x04f6" name="RBBM_PERFCTR_CMP_2_LO"/>
+ <reg32 offset="0x04f7" name="RBBM_PERFCTR_CMP_2_HI"/>
+ <reg32 offset="0x04f8" name="RBBM_PERFCTR_CMP_3_LO"/>
+ <reg32 offset="0x04f9" name="RBBM_PERFCTR_CMP_3_HI"/>
+ <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
+ <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
+ <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
+ <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
+ <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
+ <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
+ <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
+ <reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL_0"/>
+ <reg32 offset="0x0508" name="RBBM_PERFCTR_RBBM_SEL_1"/>
+ <reg32 offset="0x0509" name="RBBM_PERFCTR_RBBM_SEL_2"/>
+ <reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
+ <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
+ <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
+ <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
+ <reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
+ <reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
+ <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
+ <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
+ <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL"/>
+ <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
+ <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
+ <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD"/>
+ <reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
+ <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
+ <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
+ <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
+ <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
+ <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
+ <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
+ <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
+ <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
+ <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
+ <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
+ <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
+ <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
+ <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
+ <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
+ <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
+ <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
+ <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
+ <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
+ <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
+ <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
+ <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
+ <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
+ <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
+ <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
+ <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
+ <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
+ <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
+ <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
+ <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
+ <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
+ <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
+ <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
+ <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
+ <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
+ <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
+ <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
+ <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
+ <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
+ <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
+ <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
+ <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
+ <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
+ <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
+ <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
+ <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
+ <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
+ <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
+ <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
+ <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
+ <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
+ <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
+ <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
+ <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
+ <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
+ <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
+ <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
+ <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
+ <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
+ <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
+ <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
+ <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
+ <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
+ <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
+ <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
+ <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
+ <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
+ <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
+ <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
+ <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
+ <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
+ <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
+ <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
+ <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
+ <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
+ <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
+ <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
+ <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
+ <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
+ <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
+ <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
+ <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
+ <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
+ <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
+ <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
+ <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
+ <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
+ <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
+ <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
+ <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
+ <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
+ <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
+ <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
+ <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
+ <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
+ <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
+ <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
+ <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
+ <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
+ <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
+ <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
+ <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
+ <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
+ <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
+ <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
+ <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
+ <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
+ <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
+ <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
+ <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
+ <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
+ <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
+ <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
+ <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
+ <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
+ <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D"/>
+ <reg32 offset="0x0" name="DBGC_CFG_DBGBUS_SEL_PING_INDEX_SHIFT"/>
+ <reg32 offset="0x8" name="DBGC_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT"/>
+ <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT"/>
+ <reg32 offset="0x0" name="DBGC_CFG_DBGBUS_CNTLT_TRACEEN_SHIFT"/>
+ <reg32 offset="0xC" name="DBGC_CFG_DBGBUS_CNTLT_GRANU_SHIFT"/>
+ <reg32 offset="0x1C" name="DBGC_CFG_DBGBUS_CNTLT_SEGT_SHIFT"/>
+ <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM"/>
+ <reg32 offset="0x18" name="DBGC_CFG_DBGBUS_CTLTM_ENABLE_SHIFT"/>
+ <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
+ <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
+ <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
+ <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
+ <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
+ <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
+ <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
+ <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
+ <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0"/>
+ <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1"/>
+ <reg32 offset="0x0" name="DBGC_CFG_DBGBUS_BYTEL0_SHIFT"/>
+ <reg32 offset="0x4" name="DBGC_CFG_DBGBUS_BYTEL1_SHIFT"/>
+ <reg32 offset="0x8" name="DBGC_CFG_DBGBUS_BYTEL2_SHIFT"/>
+ <reg32 offset="0xC" name="DBGC_CFG_DBGBUS_BYTEL3_SHIFT"/>
+ <reg32 offset="0x10" name="DBGC_CFG_DBGBUS_BYTEL4_SHIFT"/>
+ <reg32 offset="0x14" name="DBGC_CFG_DBGBUS_BYTEL5_SHIFT"/>
+ <reg32 offset="0x18" name="DBGC_CFG_DBGBUS_BYTEL6_SHIFT"/>
+ <reg32 offset="0x1C" name="DBGC_CFG_DBGBUS_BYTEL7_SHIFT"/>
+ <reg32 offset="0x0" name="DBGC_CFG_DBGBUS_BYTEL8_SHIFT"/>
+ <reg32 offset="0x4" name="DBGC_CFG_DBGBUS_BYTEL9_SHIFT"/>
+ <reg32 offset="0x8" name="DBGC_CFG_DBGBUS_BYTEL10_SHIFT"/>
+ <reg32 offset="0xC" name="DBGC_CFG_DBGBUS_BYTEL11_SHIFT"/>
+ <reg32 offset="0x10" name="DBGC_CFG_DBGBUS_BYTEL12_SHIFT"/>
+ <reg32 offset="0x14" name="DBGC_CFG_DBGBUS_BYTEL13_SHIFT"/>
+ <reg32 offset="0x18" name="DBGC_CFG_DBGBUS_BYTEL14_SHIFT"/>
+ <reg32 offset="0x1C" name="DBGC_CFG_DBGBUS_BYTEL15_SHIFT"/>
+ <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
+ <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
+ <reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
+ <reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
+ <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL"/>
+ <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
+ <reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
+ <reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
+ <reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
+ <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
+ <reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
+ <reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
+ <reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
+ <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
+ <reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
+ <reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
+ <reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
+ <reg32 offset="0x8E05" name="RB_ADDR_MODE_CNTL"/>
+ <reg32 offset="0x8E08" name="RB_NC_MODE_CNTL"/>
+ <reg32 offset="0x8E10" name="RB_PERFCTR_RB_SEL_0"/>
+ <reg32 offset="0x8E11" name="RB_PERFCTR_RB_SEL_1"/>
+ <reg32 offset="0x8E12" name="RB_PERFCTR_RB_SEL_2"/>
+ <reg32 offset="0x8E13" name="RB_PERFCTR_RB_SEL_3"/>
+ <reg32 offset="0x8E14" name="RB_PERFCTR_RB_SEL_4"/>
+ <reg32 offset="0x8E15" name="RB_PERFCTR_RB_SEL_5"/>
+ <reg32 offset="0x8E16" name="RB_PERFCTR_RB_SEL_6"/>
+ <reg32 offset="0x8E17" name="RB_PERFCTR_RB_SEL_7"/>
+ <reg32 offset="0x8E18" name="RB_PERFCTR_CCU_SEL_0"/>
+ <reg32 offset="0x8E19" name="RB_PERFCTR_CCU_SEL_1"/>
+ <reg32 offset="0x8E1A" name="RB_PERFCTR_CCU_SEL_2"/>
+ <reg32 offset="0x8E1B" name="RB_PERFCTR_CCU_SEL_3"/>
+ <reg32 offset="0x8E1C" name="RB_PERFCTR_CCU_SEL_4"/>
+ <reg32 offset="0x8E2C" name="RB_PERFCTR_CMP_SEL_0"/>
+ <reg32 offset="0x8E2D" name="RB_PERFCTR_CMP_SEL_1"/>
+ <reg32 offset="0x8E2E" name="RB_PERFCTR_CMP_SEL_2"/>
+ <reg32 offset="0x8E2F" name="RB_PERFCTR_CMP_SEL_3"/>
+ <reg32 offset="0x8E50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE"/>
+ <reg32 offset="0x9E00" name="PC_DBG_ECO_CNTL"/>
+ <reg32 offset="0x9E01" name="PC_ADDR_MODE_CNTL"/>
+ <reg32 offset="0x9E34" name="PC_PERFCTR_PC_SEL_0"/>
+ <reg32 offset="0x9E35" name="PC_PERFCTR_PC_SEL_1"/>
+ <reg32 offset="0x9E36" name="PC_PERFCTR_PC_SEL_2"/>
+ <reg32 offset="0x9E37" name="PC_PERFCTR_PC_SEL_3"/>
+ <reg32 offset="0x9E38" name="PC_PERFCTR_PC_SEL_4"/>
+ <reg32 offset="0x9E39" name="PC_PERFCTR_PC_SEL_5"/>
+ <reg32 offset="0x9E3A" name="PC_PERFCTR_PC_SEL_6"/>
+ <reg32 offset="0x9E3B" name="PC_PERFCTR_PC_SEL_7"/>
+ <reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL"/>
+ <reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
+ <reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
+ <reg32 offset="0xBE12" name="HLSQ_PERFCTR_HLSQ_SEL_2"/>
+ <reg32 offset="0xBE13" name="HLSQ_PERFCTR_HLSQ_SEL_3"/>
+ <reg32 offset="0xBE14" name="HLSQ_PERFCTR_HLSQ_SEL_4"/>
+ <reg32 offset="0xBE15" name="HLSQ_PERFCTR_HLSQ_SEL_5"/>
+ <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
+ <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
+ <reg32 offset="0xA601" name="VFD_ADDR_MODE_CNTL"/>
+ <reg32 offset="0xA610" name="VFD_PERFCTR_VFD_SEL_0"/>
+ <reg32 offset="0xA611" name="VFD_PERFCTR_VFD_SEL_1"/>
+ <reg32 offset="0xA612" name="VFD_PERFCTR_VFD_SEL_2"/>
+ <reg32 offset="0xA613" name="VFD_PERFCTR_VFD_SEL_3"/>
+ <reg32 offset="0xA614" name="VFD_PERFCTR_VFD_SEL_4"/>
+ <reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/>
+ <reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/>
+ <reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/>
+ <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL"/>
+ <reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/>
+ <reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/>
+ <reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/>
+ <reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/>
+ <reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/>
+ <reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/>
+ <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL"/>
+ <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
+ <reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
+ <reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/>
+ <reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/>
+ <reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/>
+ <reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/>
+ <reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/>
+ <reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/>
+ <reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/>
+ <reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/>
+ <reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/>
+ <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/>
+ <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
+ <reg32 offset="0x0E19" name="UCHE_CLIENT_PF"/>
+ <reg32 offset="0x7" name="UCHE_CLIENT_PF_CLIENT_ID_MASK"/>
+ <reg32 offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL_0"/>
+ <reg32 offset="0x0E1D" name="UCHE_PERFCTR_UCHE_SEL_1"/>
+ <reg32 offset="0x0E1E" name="UCHE_PERFCTR_UCHE_SEL_2"/>
+ <reg32 offset="0x0E1F" name="UCHE_PERFCTR_UCHE_SEL_3"/>
+ <reg32 offset="0x0E20" name="UCHE_PERFCTR_UCHE_SEL_4"/>
+ <reg32 offset="0x0E21" name="UCHE_PERFCTR_UCHE_SEL_5"/>
+ <reg32 offset="0x0E22" name="UCHE_PERFCTR_UCHE_SEL_6"/>
+ <reg32 offset="0x0E23" name="UCHE_PERFCTR_UCHE_SEL_7"/>
+ <reg32 offset="0x0E24" name="UCHE_PERFCTR_UCHE_SEL_8"/>
+ <reg32 offset="0x0E25" name="UCHE_PERFCTR_UCHE_SEL_9"/>
+ <reg32 offset="0x0E26" name="UCHE_PERFCTR_UCHE_SEL_10"/>
+ <reg32 offset="0x0E27" name="UCHE_PERFCTR_UCHE_SEL_11"/>
+ <reg32 offset="0xAE01" name="SP_ADDR_MODE_CNTL"/>
+ <reg32 offset="0xAE02" name="SP_NC_MODE_CNTL"/>
+ <reg32 offset="0xAE10" name="SP_PERFCTR_SP_SEL_0"/>
+ <reg32 offset="0xAE11" name="SP_PERFCTR_SP_SEL_1"/>
+ <reg32 offset="0xAE12" name="SP_PERFCTR_SP_SEL_2"/>
+ <reg32 offset="0xAE13" name="SP_PERFCTR_SP_SEL_3"/>
+ <reg32 offset="0xAE14" name="SP_PERFCTR_SP_SEL_4"/>
+ <reg32 offset="0xAE15" name="SP_PERFCTR_SP_SEL_5"/>
+ <reg32 offset="0xAE16" name="SP_PERFCTR_SP_SEL_6"/>
+ <reg32 offset="0xAE17" name="SP_PERFCTR_SP_SEL_7"/>
+ <reg32 offset="0xAE18" name="SP_PERFCTR_SP_SEL_8"/>
+ <reg32 offset="0xAE19" name="SP_PERFCTR_SP_SEL_9"/>
+ <reg32 offset="0xAE1A" name="SP_PERFCTR_SP_SEL_10"/>
+ <reg32 offset="0xAE1B" name="SP_PERFCTR_SP_SEL_11"/>
+ <reg32 offset="0xAE1C" name="SP_PERFCTR_SP_SEL_12"/>
+ <reg32 offset="0xAE1D" name="SP_PERFCTR_SP_SEL_13"/>
+ <reg32 offset="0xAE1E" name="SP_PERFCTR_SP_SEL_14"/>
+ <reg32 offset="0xAE1F" name="SP_PERFCTR_SP_SEL_15"/>
+ <reg32 offset="0xAE20" name="SP_PERFCTR_SP_SEL_16"/>
+ <reg32 offset="0xAE21" name="SP_PERFCTR_SP_SEL_17"/>
+ <reg32 offset="0xAE22" name="SP_PERFCTR_SP_SEL_18"/>
+ <reg32 offset="0xAE23" name="SP_PERFCTR_SP_SEL_19"/>
+ <reg32 offset="0xAE24" name="SP_PERFCTR_SP_SEL_20"/>
+ <reg32 offset="0xAE25" name="SP_PERFCTR_SP_SEL_21"/>
+ <reg32 offset="0xAE26" name="SP_PERFCTR_SP_SEL_22"/>
+ <reg32 offset="0xAE27" name="SP_PERFCTR_SP_SEL_23"/>
+ <reg32 offset="0xB601" name="TPL1_ADDR_MODE_CNTL"/>
+ <reg32 offset="0xB604" name="TPL1_NC_MODE_CNTL"/>
+ <reg32 offset="0xB610" name="TPL1_PERFCTR_TP_SEL_0"/>
+ <reg32 offset="0xB611" name="TPL1_PERFCTR_TP_SEL_1"/>
+ <reg32 offset="0xB612" name="TPL1_PERFCTR_TP_SEL_2"/>
+ <reg32 offset="0xB613" name="TPL1_PERFCTR_TP_SEL_3"/>
+ <reg32 offset="0xB614" name="TPL1_PERFCTR_TP_SEL_4"/>
+ <reg32 offset="0xB615" name="TPL1_PERFCTR_TP_SEL_5"/>
+ <reg32 offset="0xB616" name="TPL1_PERFCTR_TP_SEL_6"/>
+ <reg32 offset="0xB617" name="TPL1_PERFCTR_TP_SEL_7"/>
+ <reg32 offset="0xB618" name="TPL1_PERFCTR_TP_SEL_8"/>
+ <reg32 offset="0xB619" name="TPL1_PERFCTR_TP_SEL_9"/>
+ <reg32 offset="0xB61A" name="TPL1_PERFCTR_TP_SEL_10"/>
+ <reg32 offset="0xB61B" name="TPL1_PERFCTR_TP_SEL_11"/>
+ <reg32 offset="0x3000" name="VBIF_VERSION"/>
+ <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
+ <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
+ <reg32 offset="0xF" name="VBIF_XIN_HALT_CTRL0_MASK"/>
+ <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
+ <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
+ <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
+ <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
+ <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
+ <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
+ <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
+ <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
+ <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
+ <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
+ <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
+ <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
+ <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
+ <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
+ <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
+ <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
+ <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
+ <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
+ <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
+ <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
+ <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
+ <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
+ <reg32 offset="0x18400" name="CX_DBGC_CFG_DBGBUS_SEL_A"/>
+ <reg32 offset="0x18401" name="CX_DBGC_CFG_DBGBUS_SEL_B"/>
+ <reg32 offset="0x18402" name="CX_DBGC_CFG_DBGBUS_SEL_C"/>
+ <reg32 offset="0x18403" name="CX_DBGC_CFG_DBGBUS_SEL_D"/>
+ <reg32 offset="0x18404" name="CX_DBGC_CFG_DBGBUS_CNTLT"/>
+ <reg32 offset="0x0" name="CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN_SHIFT"/>
+ <reg32 offset="0xC" name="CX_DBGC_CFG_DBGBUS_CNTLT_GRANU_SHIFT"/>
+ <reg32 offset="0x1C" name="CX_DBGC_CFG_DBGBUS_CNTLT_SEGT_SHIFT"/>
+ <reg32 offset="0x18405" name="CX_DBGC_CFG_DBGBUS_CNTLM"/>
+ <reg32 offset="0x18" name="CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE_SHIFT"/>
+ <reg32 offset="0x18408" name="CX_DBGC_CFG_DBGBUS_IVTL_0"/>
+ <reg32 offset="0x18409" name="CX_DBGC_CFG_DBGBUS_IVTL_1"/>
+ <reg32 offset="0x1840A" name="CX_DBGC_CFG_DBGBUS_IVTL_2"/>
+ <reg32 offset="0x1840B" name="CX_DBGC_CFG_DBGBUS_IVTL_3"/>
+ <reg32 offset="0x1840C" name="CX_DBGC_CFG_DBGBUS_MASKL_0"/>
+ <reg32 offset="0x1840D" name="CX_DBGC_CFG_DBGBUS_MASKL_1"/>
+ <reg32 offset="0x1840E" name="CX_DBGC_CFG_DBGBUS_MASKL_2"/>
+ <reg32 offset="0x1840F" name="CX_DBGC_CFG_DBGBUS_MASKL_3"/>
+ <reg32 offset="0x18410" name="CX_DBGC_CFG_DBGBUS_BYTEL_0"/>
+ <reg32 offset="0x18411" name="CX_DBGC_CFG_DBGBUS_BYTEL_1"/>
+ <reg32 offset="0x0" name="CX_DBGC_CFG_DBGBUS_BYTEL0_SHIFT"/>
+ <reg32 offset="0x4" name="CX_DBGC_CFG_DBGBUS_BYTEL1_SHIFT"/>
+ <reg32 offset="0x8" name="CX_DBGC_CFG_DBGBUS_BYTEL2_SHIFT"/>
+ <reg32 offset="0xC" name="CX_DBGC_CFG_DBGBUS_BYTEL3_SHIFT"/>
+ <reg32 offset="0x10" name="CX_DBGC_CFG_DBGBUS_BYTEL4_SHIFT"/>
+ <reg32 offset="0x14" name="CX_DBGC_CFG_DBGBUS_BYTEL5_SHIFT"/>
+ <reg32 offset="0x18" name="CX_DBGC_CFG_DBGBUS_BYTEL6_SHIFT"/>
+ <reg32 offset="0x1C" name="CX_DBGC_CFG_DBGBUS_BYTEL7_SHIFT"/>
+ <reg32 offset="0x0" name="CX_DBGC_CFG_DBGBUS_BYTEL8_SHIFT"/>
+ <reg32 offset="0x4" name="CX_DBGC_CFG_DBGBUS_BYTEL9_SHIFT"/>
+ <reg32 offset="0x8" name="CX_DBGC_CFG_DBGBUS_BYTEL10_SHIFT"/>
+ <reg32 offset="0xC" name="CX_DBGC_CFG_DBGBUS_BYTEL11_SHIFT"/>
+ <reg32 offset="0x10" name="CX_DBGC_CFG_DBGBUS_BYTEL12_SHIFT"/>
+ <reg32 offset="0x14" name="CX_DBGC_CFG_DBGBUS_BYTEL13_SHIFT"/>
+ <reg32 offset="0x18" name="CX_DBGC_CFG_DBGBUS_BYTEL14_SHIFT"/>
+ <reg32 offset="0x1C" name="CX_DBGC_CFG_DBGBUS_BYTEL15_SHIFT"/>
+ <reg32 offset="0x1842F" name="CX_DBGC_CFG_DBGBUS_TRACE_BUF1"/>
+ <reg32 offset="0x18430" name="CX_DBGC_CFG_DBGBUS_TRACE_BUF2"/>
+ <reg32 offset="0x0" name="CX_DBGC_CFG_DBGBUS_SEL_PING_INDEX_SHIFT"/>
+ <reg32 offset="0x8" name="CX_DBGC_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT"/>
+ <reg32 offset="0x21140" name="PDC_GPU_ENABLE_PDC"/>
+ <reg32 offset="0x21148" name="PDC_GPU_SEQ_START_ADDR"/>
+ <reg32 offset="0x21540" name="PDC_GPU_TCS0_CONTROL"/>
+ <reg32 offset="0x21541" name="PDC_GPU_TCS0_CMD_ENABLE_BANK"/>
+ <reg32 offset="0x21542" name="PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
+ <reg32 offset="0x21543" name="PDC_GPU_TCS0_CMD0_MSGID"/>
+ <reg32 offset="0x21544" name="PDC_GPU_TCS0_CMD0_ADDR"/>
+ <reg32 offset="0x21545" name="PDC_GPU_TCS0_CMD0_DATA"/>
+ <reg32 offset="0x21572" name="PDC_GPU_TCS1_CONTROL"/>
+ <reg32 offset="0x21573" name="PDC_GPU_TCS1_CMD_ENABLE_BANK"/>
+ <reg32 offset="0x21574" name="PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
+ <reg32 offset="0x21575" name="PDC_GPU_TCS1_CMD0_MSGID"/>
+ <reg32 offset="0x21576" name="PDC_GPU_TCS1_CMD0_ADDR"/>
+ <reg32 offset="0x21577" name="PDC_GPU_TCS1_CMD0_DATA"/>
+ <reg32 offset="0x215A4" name="PDC_GPU_TCS2_CONTROL"/>
+ <reg32 offset="0x215A5" name="PDC_GPU_TCS2_CMD_ENABLE_BANK"/>
+ <reg32 offset="0x215A6" name="PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
+ <reg32 offset="0x215A7" name="PDC_GPU_TCS2_CMD0_MSGID"/>
+ <reg32 offset="0x215A8" name="PDC_GPU_TCS2_CMD0_ADDR"/>
+ <reg32 offset="0x215A9" name="PDC_GPU_TCS2_CMD0_DATA"/>
+ <reg32 offset="0x215D6" name="PDC_GPU_TCS3_CONTROL"/>
+ <reg32 offset="0x215D7" name="PDC_GPU_TCS3_CMD_ENABLE_BANK"/>
+ <reg32 offset="0x215D8" name="PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
+ <reg32 offset="0x215D9" name="PDC_GPU_TCS3_CMD0_MSGID"/>
+ <reg32 offset="0x215DA" name="PDC_GPU_TCS3_CMD0_ADDR"/>
+ <reg32 offset="0x215DB" name="PDC_GPU_TCS3_CMD0_DATA"/>
+ <reg32 offset="0xA0000" name="PDC_GPU_SEQ_MEM_0"/>
+
+</domain>
+
+</database>
diff --git a/rnndb/adreno/a6xx_gmu.xml b/rnndb/adreno/a6xx_gmu.xml
new file mode 100644
index 0000000..4a212d5
--- /dev/null
+++ b/rnndb/adreno/a6xx_gmu.xml
@@ -0,0 +1,211 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
+<import file="freedreno_copyright.xml"/>
+
+<domain name="A6XX" width="32">
+
+ <bitset name="A6XX_GMU_GPU_IDLE_STATUS">
+ <bitfield name="BUSY_IGN_AHB" pos="23"/>
+ <bitfield name="CX_GX_CPU_BUSY_IGN_AHB" pos="30"/>
+ </bitset>
+
+ <bitset name="A6XX_GMU_OOB">
+ <bitfield name="BOOT_SLUMBER_SET_MASK" pos="22"/>
+ <bitfield name="BOOT_SLUMBER_CHECK_MASK" pos="30"/>
+ <bitfield name="BOOT_SLUMBER_CLEAR_MASK" pos="30"/>
+ <bitfield name="DCVS_SET_MASK" pos="23"/>
+ <bitfield name="DCVS_CHECK_MASK" pos="31"/>
+ <bitfield name="DCVS_CLEAR_MASK" pos="31"/>
+ <bitfield name="GPU_SET_MASK" pos="18"/>
+ <bitfield name="GPU_CHECK_MASK" pos="26"/>
+ <bitfield name="GPU_CLEAR_MASK" pos="26"/>
+ <bitfield name="PERFCNTR_SET_MASK" pos="17"/>
+ <bitfield name="PERFCNTR_CHECK_MASK" pos="25"/>
+ <bitfield name="PERFCNTR_CLEAR_MASK" pos="25"/>
+ </bitset>
+
+ <bitset name="A6XX_HFI_IRQ">
+ <bitfield name="MSGQ_MASK" pos="0" />
+ <bitfield name="DSGQ_MASK" pos="1"/>
+ <bitfield name="BLOCKED_MSG_MASK" pos="2"/>
+ <bitfield name="CM3_FAULT_MASK" pos="23"/>
+ <bitfield name="GMU_ERR_MASK" low="16" high="22"/>
+ <bitfield name="OOB_MASK" low="24" high="31"/>
+ </bitset>
+
+ <bitset name="A6XX_HFI_H2F">
+ <bitfield name="IRQ_MASK_BIT" pos="0" />
+ </bitset>
+
+ <reg32 offset="0x80" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
+ <reg32 offset="0x81" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
+ <reg32 offset="0xc00" name="GMU_CM3_ITCM_START"/>
+ <reg32 offset="0x1c00" name="GMU_CM3_DTCM_START"/>
+ <reg32 offset="0x23f0" name="GMU_NMI_CONTROL_STATUS"/>
+ <reg32 offset="0x23f8" name="GMU_BOOT_SLUMBER_OPTION"/>
+ <reg32 offset="0x23f9" name="GMU_GX_VOTE_IDX"/>
+ <reg32 offset="0x23fa" name="GMU_MX_VOTE_IDX"/>
+ <reg32 offset="0x23fc" name="GMU_DCVS_ACK_OPTION"/>
+ <reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/>
+ <reg32 offset="0x23fe" name="GMU_DCVS_BW_SETTING"/>
+ <reg32 offset="0x23ff" name="GMU_DCVS_RETURN"/>
+ <reg32 offset="0x4c0f" name="GMU_SYS_BUS_CONFIG"/>
+ <reg32 offset="0x5000" name="GMU_CM3_SYSRESET"/>
+ <reg32 offset="0x5001" name="GMU_CM3_BOOT_CONFIG"/>
+ <reg32 offset="0x501a" name="GMU_CM3_FW_BUSY"/>
+ <reg32 offset="0x501c" name="GMU_CM3_FW_INIT_RESULT"/>
+ <reg32 offset="0x502d" name="GMU_CM3_CFG"/>
+ <reg32 offset="0x5040" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/>
+ <reg32 offset="0x5041" name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/>
+ <reg32 offset="0x5042" name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/>
+ <reg32 offset="0x5044" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/>
+ <reg32 offset="0x5045" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/>
+ <reg32 offset="0x5046" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/>
+ <reg32 offset="0x5047" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/>
+ <reg32 offset="0x5048" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/>
+ <reg32 offset="0x5049" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H"/>
+ <reg32 offset="0x504a" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L"/>
+ <reg32 offset="0x504b" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H"/>
+ <reg32 offset="0x504c" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L"/>
+ <reg32 offset="0x504d" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H"/>
+ <reg32 offset="0x504e" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L"/>
+ <reg32 offset="0x504f" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H"/>
+ <reg32 offset="0x50c0" name="GMU_PWR_COL_INTER_FRAME_CTRL">
+ <bitfield name="IFPC_ENABLE" pos="0"/>
+ <bitfield name="HM_POWER_COLLAPSE_ENABLE" pos="1"/>
+ <bitfield name="SPTPRAC_POWER_CONTROL_ENABLE" pos="2"/>
+ <bitfield name="NUM_PASS_SKIPS" low="10" high="13"/>
+ <bitfield name="MIN_PASS_LENGTH" low="14" high="31"/>
+ </reg32>
+ <reg32 offset="0x50c1" name="GMU_PWR_COL_INTER_FRAME_HYST"/>
+ <reg32 offset="0x50c2" name="GMU_PWR_COL_SPTPRAC_HYST"/>
+ <reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS">
+ <bitfield name="SPTPRAC_GDSC_POWERING_OFF" pos="0"/>
+ <bitfield name="SPTPRAC_GDSC_POWERING_ON" pos="1"/>
+ <bitfield name="SPTPRAC_GDSC_POWER_ON" pos="2"/>
+ <bitfield name="SPTPRAC_GDSC_POWER_OFF" pos="3"/>
+ <bitfield name="SP_CLOCK_OFF" pos="4"/>
+ <bitfield name="GMU_UP_POWER_STATE" pos="5"/>
+ <bitfield name="GX_HM_GDSC_POWER_OFF" pos="6"/>
+ <bitfield name="GX_HM_CLK_OFF" pos="7"/>
+ </reg32>
+ <reg32 offset="0x50e4" name="GMU_GPU_NAP_CTRL">
+ <bitfield name="HW_NAP_ENABLE" pos="0"/>
+ <bitfield name="SID" low="4" high="8"/>
+ </reg32>
+ <reg32 offset="0x50e8" name="GMU_RPMH_CTRL">
+ <bitfield name="RPMH_INTERFACE_ENABLE" pos="0"/>
+ <bitfield name="LLC_VOTE_ENABLE" pos="4"/>
+ <bitfield name="DDR_VOTE_ENABLE" pos="8"/>
+ <bitfield name="MX_VOTE_ENABLE" pos="9"/>
+ <bitfield name="CX_VOTE_ENABLE" pos="10"/>
+ <bitfield name="GFX_VOTE_ENABLE" pos="11"/>
+ <bitfield name="DDR_MIN_VOTE_ENABLE" pos="12"/>
+ <bitfield name="MX_MIN_VOTE_ENABLE" pos="13"/>
+ <bitfield name="CX_MIN_VOTE_ENABLE" pos="14"/>
+ <bitfield name="GFX_MIN_VOTE_ENABLE" pos="15"/>
+ </reg32>
+ <reg32 offset="0x50e9" name="GMU_RPMH_HYST_CTRL"/>
+ <reg32 offset="0x50ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE"/>
+ <reg32 offset="0x51f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
+ <reg32 offset="0x5157" name="GMU_LLM_GLM_SLEEP_CTRL"/>
+ <reg32 offset="0x5158" name="GMU_LLM_GLM_SLEEP_STATUS"/>
+ <reg32 offset="0x5088" name="GMU_ALWAYS_ON_COUNTER_L"/>
+ <reg32 offset="0x5089" name="GMU_ALWAYS_ON_COUNTER_H"/>
+ <reg32 offset="0x50c3" name="GMU_GMU_PWR_COL_KEEPALIVE"/>
+ <reg32 offset="0x5180" name="GMU_HFI_CTRL_STATUS"/>
+ <reg32 offset="0x5181" name="GMU_HFI_VERSION_INFO"/>
+ <reg32 offset="0x5182" name="GMU_HFI_SFR_ADDR"/>
+ <reg32 offset="0x5183" name="GMU_HFI_MMAP_ADDR"/>
+ <reg32 offset="0x5184" name="GMU_HFI_QTBL_INFO"/>
+ <reg32 offset="0x5185" name="GMU_HFI_QTBL_ADDR"/>
+ <reg32 offset="0x5186" name="GMU_HFI_CTRL_INIT"/>
+ <reg32 offset="0x5190" name="GMU_GMU2HOST_INTR_SET"/>
+ <reg32 offset="0x5191" name="GMU_GMU2HOST_INTR_CLR"/>
+ <reg32 offset="0x5192" name="GMU_GMU2HOST_INTR_INFO">
+ <bitfield name="MSGQ" pos="0"/>
+ <bitfield name="CM3_FAULT" pos="23"/>
+ </reg32>
+ <reg32 offset="0x5193" name="GMU_GMU2HOST_INTR_MASK"/>
+ <reg32 offset="0x5194" name="GMU_HOST2GMU_INTR_SET"/>
+ <reg32 offset="0x5195" name="GMU_HOST2GMU_INTR_CLR"/>
+ <reg32 offset="0x5196" name="GMU_HOST2GMU_INTR_RAW_INFO"/>
+ <reg32 offset="0x5197" name="GMU_HOST2GMU_INTR_EN_0"/>
+ <reg32 offset="0x5198" name="GMU_HOST2GMU_INTR_EN_1"/>
+ <reg32 offset="0x5199" name="GMU_HOST2GMU_INTR_EN_2"/>
+ <reg32 offset="0x519a" name="GMU_HOST2GMU_INTR_EN_3"/>
+ <reg32 offset="0x519b" name="GMU_HOST2GMU_INTR_INFO_0"/>
+ <reg32 offset="0x519c" name="GMU_HOST2GMU_INTR_INFO_1"/>
+ <reg32 offset="0x519d" name="GMU_HOST2GMU_INTR_INFO_2"/>
+ <reg32 offset="0x519e" name="GMU_HOST2GMU_INTR_INFO_3"/>
+ <reg32 offset="0x51c6" name="GMU_GENERAL_1"/>
+ <reg32 offset="0x51cc" name="GMU_GENERAL_7"/>
+ <reg32 offset="0x515d" name="GMU_ISENSE_CTRL"/>
+ <reg32 offset="0x8920" name="GPU_CS_ENABLE_REG"/>
+ <reg32 offset="0x515d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/>
+ <reg32 offset="0x8578" name="GPU_CS_AMP_CALIBRATION_CONTROL3"/>
+ <reg32 offset="0x8558" name="GPU_CS_AMP_CALIBRATION_CONTROL2"/>
+ <reg32 offset="0x8580" name="GPU_CS_A_SENSOR_CTRL_0"/>
+ <reg32 offset="0x27ada" name="GPU_CS_A_SENSOR_CTRL_2"/>
+ <reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
+ <reg32 offset="0x8957" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
+ <reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
+ <reg32 offset="0x881d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
+ <reg32 offset="0x881f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
+ <reg32 offset="0x8821" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
+ <reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
+ <reg32 offset="0x896d" name="GPU_CS_AMP_PERIOD_CTRL"/>
+ <reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
+ <reg32 offset="0x514d" name="GPU_GMU_CX_GMU_PWR_THRESHOLD"/>
+ <reg32 offset="0x9303" name="GMU_AO_INTERRUPT_EN"/>
+ <reg32 offset="0x9304" name="GMU_AO_HOST_INTERRUPT_CLR"/>
+ <reg32 offset="0x9305" name="GMU_AO_HOST_INTERRUPT_STATUS">
+ <bitfield name="WDOG_BITE" pos="0"/>
+ <bitfield name="RSCC_COMP" pos="1"/>
+ <bitfield name="VDROOP" pos="2"/>
+ <bitfield name="FENCE_ERR" pos="3"/>
+ <bitfield name="DBD_WAKEUP" pos="4"/>
+ <bitfield name="HOST_AHB_BUS_ERROR" pos="5"/>
+ </reg32>
+ <reg32 offset="0x9306" name="GMU_AO_HOST_INTERRUPT_MASK"/>
+ <reg32 offset="0x9309" name="GPU_GMU_AO_GMU_CGC_MODE_CNTL"/>
+ <reg32 offset="0x930a" name="GPU_GMU_AO_GMU_CGC_DELAY_CNTL"/>
+ <reg32 offset="0x930b" name="GPU_GMU_AO_GMU_CGC_HYST_CNTL"/>
+ <reg32 offset="0x930c" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS">
+ <bitfield name = "GPUBUSYIGNAHB" pos="23"/>
+ </reg32>
+ <reg32 offset="0x930d" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS2"/>
+ <reg32 offset="0x930e" name="GPU_GMU_AO_GPU_CX_BUSY_MASK"/>
+ <reg32 offset="0x9310" name="GMU_AO_AHB_FENCE_CTRL"/>
+ <reg32 offset="0x9313" name="GMU_AHB_FENCE_STATUS"/>
+ <reg32 offset="0x9315" name="GMU_RBBM_INT_UNMASKED_STATUS"/>
+ <reg32 offset="0x9316" name="GMU_AO_SPARE_CNTL"/>
+ <reg32 offset="0x8c04" name="GPU_RSCC_RSC_STATUS0_DRV0"/>
+ <reg32 offset="0x9307" name="GMU_RSCC_CONTROL_REQ"/>
+ <reg32 offset="0x9308" name="GMU_RSCC_CONTROL_ACK"/>
+ <reg32 offset="0x9311" name="GMU_AHB_FENCE_RANGE_0"/>
+ <reg32 offset="0x9312" name="GMU_AHB_FENCE_RANGE_1"/>
+ <reg32 offset="0x9c03" name="GPU_CC_GX_GDSCR"/>
+ <reg32 offset="0x9d42" name="GPU_CC_GX_DOMAIN_MISC"/>
+ <reg32 offset="0x8c08" name="RSCC_PDC_SEQ_START_ADDR"/>
+ <reg32 offset="0x8c09" name="RSCC_PDC_MATCH_VALUE_LO"/>
+ <reg32 offset="0x8c0a" name="RSCC_PDC_MATCH_VALUE_HI"/>
+ <reg32 offset="0x8c0b" name="RSCC_PDC_SLAVE_ID_DRV0"/>
+ <reg32 offset="0x8c0d" name="RSCC_HIDDEN_TCS_CMD0_ADDR"/>
+ <reg32 offset="0x8c0e" name="RSCC_HIDDEN_TCS_CMD0_DATA"/>
+ <reg32 offset="0x8c82" name="RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0"/>
+ <reg32 offset="0x8c83" name="RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0"/>
+ <reg32 offset="0x8c89" name="RSCC_TIMESTAMP_UNIT1_EN_DRV0"/>
+ <reg32 offset="0x8c8c" name="RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0"/>
+ <reg32 offset="0x8d00" name="RSCC_OVERRIDE_START_ADDR"/>
+ <reg32 offset="0x8d01" name="RSCC_SEQ_BUSY_DRV0"/>
+ <reg32 offset="0x8d80" name="RSCC_SEQ_MEM_0_DRV0"/>
+ <reg32 offset="0x8f46" name="RSCC_TCS0_DRV0_STATUS"/>
+ <reg32 offset="0x90ae" name="RSCC_TCS1_DRV0_STATUS"/>
+ <reg32 offset="0x9216" name="RSCC_TCS2_DRV0_STATUS"/>
+ <reg32 offset="0x937e" name="RSCC_TCS3_DRV0_STATUS"/>
+</domain>
+
+</database>
--
1.9.1
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