[Freedreno] [PATCH 11/21] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor

[Archit Taneja]

On Monday 09 July 2018 11:01 PM, Sean Paul wrote:
> From: Abhinav Kumar <abhinavk at codeaurora.org>
> 
> Make the pclk_rate u64 to accommodate higher pixel clock
> rates.
> 
> Changes in v4:
>   - fixed commit message
> 
> Signed-off-by: Abhinav Kumar <abhinavk at codeaurora.org>
> Signed-off-by: Sean Paul <seanpaul at chromium.org>
> ---
>   drivers/gpu/drm/msm/dsi/dsi_host.c | 9 ++++++---
>   1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 671039b7b75b..73587e731a23 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -669,7 +669,8 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi)
>   	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
>   	u8 lanes = msm_host->lanes;
>   	u32 bpp = dsi_get_bpp(msm_host->format);
> -	u32 pclk_rate;
> +	u64 pclk_rate;
> +	u64 pclk_bpp;
>   

Minor nit, I don't think we need to change pclk_rate to u64. A u32 can
hold up to a 2.14 Ghz pixel clock, which we're still quite far away
from in real life. u64 for pclk_bpp is right, though.

Thanks,
Archit

>   	if (!mode) {
>   		pr_err("%s: mode not set\n", __func__);
> @@ -689,13 +690,15 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi)
>   	if (is_dual_dsi)
>   		pclk_rate /= 2;
>   
> +	pclk_bpp = pclk_rate * bpp;
>   	if (lanes > 0) {
> -		msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
> +		do_div(pclk_bpp, (8 * lanes));
>   	} else {
>   		pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
> -		msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
> +		do_div(pclk_bpp, 8);
>   	}
>   	msm_host->pixel_clk_rate = pclk_rate;
> +	msm_host->byte_clk_rate = pclk_bpp;
>   
>   	DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,
>   				msm_host->byte_clk_rate);
>