[Freedreno] [DPU PATCH] drm/msm: remove hw rotation support
Sean Paul
seanpaul at chromium.org
Fri Mar 2 17:05:29 UTC 2018
On Thu, Mar 01, 2018 at 06:15:47PM -0800, Jeykumar Sankaran wrote:
> Remove HW inline rotation support from DPU driver.
>
> Signed-off-by: Jeykumar Sankaran <jsanka at codeaurora.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 126 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 33 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 17 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 10 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 4 -
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 72 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 188 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 59 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 51 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 36 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 21 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 4 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 13 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.c | 961 -------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.h | 190 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 49 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 66 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 1416 +-------------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 77 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 22 -
> drivers/gpu/drm/msm/msm_drv.h | 11 +-
> 21 files changed, 37 insertions(+), 3389 deletions(-)
> delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.c
> delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.h
This doesn't apply cleanly to for-next-staging, can you please rebase?
Sean
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index ab36578..319b51f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -822,12 +822,11 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
> struct dpu_hw_stage_cfg *stage_cfg;
> struct dpu_rect plane_crtc_roi;
>
> - u32 flush_mask, flush_sbuf;
> + u32 flush_mask;
> uint32_t stage_idx, lm_idx;
> int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 };
> int i;
> bool bg_alpha_enable = false;
> - u32 prefill = 0;
>
> if (!dpu_crtc || !mixer) {
> DPU_ERROR("invalid dpu_crtc or mixer\n");
> @@ -839,9 +838,6 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
> stage_cfg = &dpu_crtc->stage_cfg;
> cstate = to_dpu_crtc_state(crtc->state);
>
> - cstate->sbuf_prefill_line = 0;
> - dpu_crtc->sbuf_flush_mask = 0x0;
> -
> drm_atomic_crtc_for_each_plane(plane, crtc) {
> state = plane->state;
> if (!state)
> @@ -855,14 +851,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
> pstate = to_dpu_plane_state(state);
> fb = state->fb;
>
> - prefill = dpu_plane_rot_calc_prefill(plane);
> - if (prefill > cstate->sbuf_prefill_line)
> - cstate->sbuf_prefill_line = prefill;
> -
> - dpu_plane_get_ctl_flush(plane, ctl, &flush_mask, &flush_sbuf);
> -
> - /* save sbuf flush value for later */
> - dpu_crtc->sbuf_flush_mask |= flush_sbuf;
> + dpu_plane_get_ctl_flush(plane, ctl, &flush_mask);
>
> DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
> crtc->base.id,
> @@ -885,8 +874,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
> state->src_x >> 16, state->src_y >> 16,
> state->src_w >> 16, state->src_h >> 16,
> state->crtc_x, state->crtc_y,
> - state->crtc_w, state->crtc_h,
> - flush_sbuf != 0);
> + state->crtc_w, state->crtc_h);
>
> stage_idx = zpos_cnt[pstate->stage]++;
> stage_cfg->stage[pstate->stage][stage_idx] =
> @@ -2387,64 +2375,6 @@ static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc)
> return rc;
> }
>
> -static void _dpu_crtc_commit_kickoff_rot(struct drm_crtc *crtc,
> - struct dpu_crtc_state *cstate)
> -{
> - struct drm_plane *plane;
> - struct dpu_crtc *dpu_crtc;
> - struct dpu_hw_ctl *ctl, *master_ctl;
> - u32 flush_mask;
> - int i;
> -
> - if (!crtc || !cstate)
> - return;
> -
> - dpu_crtc = to_dpu_crtc(crtc);
> -
> - /*
> - * Update sbuf configuration and flush bits if a flush
> - * mask has been defined for either the current or
> - * previous commit.
> - *
> - * Updates are also required for the first commit after
> - * sbuf_flush_mask becomes 0x0, to properly transition
> - * the hardware out of sbuf mode.
> - */
> - if (!dpu_crtc->sbuf_flush_mask_old && !dpu_crtc->sbuf_flush_mask)
> - return;
> -
> - flush_mask = dpu_crtc->sbuf_flush_mask_old | dpu_crtc->sbuf_flush_mask;
> - dpu_crtc->sbuf_flush_mask_old = dpu_crtc->sbuf_flush_mask;
> -
> - DPU_ATRACE_BEGIN("crtc_kickoff_rot");
> -
> - if (cstate->sbuf_cfg.rot_op_mode != DPU_CTL_ROT_OP_MODE_OFFLINE) {
> - drm_atomic_crtc_for_each_plane(plane, crtc) {
> - dpu_plane_kickoff(plane);
> - }
> - }
> -
> - master_ctl = NULL;
> - for (i = 0; i < dpu_crtc->num_mixers; i++) {
> - ctl = dpu_crtc->mixers[i].hw_ctl;
> - if (!ctl || !ctl->ops.setup_sbuf_cfg ||
> - !ctl->ops.update_pending_flush)
> - continue;
> -
> - if (!master_ctl || master_ctl->idx > ctl->idx)
> - master_ctl = ctl;
> -
> - ctl->ops.setup_sbuf_cfg(ctl, &cstate->sbuf_cfg);
> - ctl->ops.update_pending_flush(ctl, flush_mask);
> - }
> -
> - if (cstate->sbuf_cfg.rot_op_mode == DPU_CTL_ROT_OP_MODE_INLINE_ASYNC &&
> - master_ctl && master_ctl->ops.trigger_rot_start)
> - master_ctl->ops.trigger_rot_start(master_ctl);
> -
> - DPU_ATRACE_END("crtc_kickoff_rot");
> -}
> -
> void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
> {
> struct drm_encoder *encoder;
> @@ -2481,10 +2411,6 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
>
> DPU_ATRACE_BEGIN("crtc_commit");
>
> - /* default to ASYNC mode for inline rotation */
> - cstate->sbuf_cfg.rot_op_mode = dpu_crtc->sbuf_flush_mask ?
> - DPU_CTL_ROT_OP_MODE_INLINE_ASYNC : DPU_CTL_ROT_OP_MODE_OFFLINE;
> -
> list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
> struct dpu_encoder_kickoff_params params = { 0 };
>
> @@ -2495,29 +2421,9 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
> * Encoder will flush/start now, unless it has a tx pending.
> * If so, it may delay and flush at an irq event (e.g. ppdone)
> */
> - params.inline_rotate_prefill = cstate->sbuf_prefill_line;
> dpu_encoder_prepare_for_kickoff(encoder, ¶ms);
> -
> - /*
> - * For inline ASYNC modes, the flush bits are not written
> - * to hardware atomically, so avoid using it if a video
> - * mode encoder is active on this CRTC.
> - */
> - if (cstate->sbuf_cfg.rot_op_mode ==
> - DPU_CTL_ROT_OP_MODE_INLINE_ASYNC &&
> - dpu_encoder_get_intf_mode(encoder) ==
> - INTF_MODE_VIDEO)
> - cstate->sbuf_cfg.rot_op_mode =
> - DPU_CTL_ROT_OP_MODE_INLINE_SYNC;
> }
>
> - /*
> - * For ASYNC inline modes, kick off the rotator now so that the H/W
> - * can start as soon as it's ready.
> - */
> - if (cstate->sbuf_cfg.rot_op_mode == DPU_CTL_ROT_OP_MODE_INLINE_ASYNC)
> - _dpu_crtc_commit_kickoff_rot(crtc, cstate);
> -
> /* wait for frame_event_done completion */
> DPU_ATRACE_BEGIN("wait_for_frame_done_event");
> ret = _dpu_crtc_wait_for_frame_done(crtc);
> @@ -2532,24 +2438,10 @@ void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
> if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) {
> /* acquire bandwidth and other resources */
> DPU_DEBUG("crtc%d first commit\n", crtc->base.id);
> - DPU_EVT32(DRMID(crtc), cstate->sbuf_cfg.rot_op_mode,
> - DPU_EVTLOG_FUNC_CASE1);
> - } else {
> + } else
> DPU_DEBUG("crtc%d commit\n", crtc->base.id);
> - DPU_EVT32(DRMID(crtc), cstate->sbuf_cfg.rot_op_mode,
> - DPU_EVTLOG_FUNC_CASE2);
> - }
> - dpu_crtc->play_count++;
>
> - /*
> - * For SYNC inline modes, delay the kick off until after the
> - * wait for frame done in case the wait times out.
> - *
> - * Also perform a final kickoff when transitioning back to
> - * offline mode.
> - */
> - if (cstate->sbuf_cfg.rot_op_mode != DPU_CTL_ROT_OP_MODE_INLINE_ASYNC)
> - _dpu_crtc_commit_kickoff_rot(crtc, cstate);
> + dpu_crtc->play_count++;
>
> dpu_vbif_clear_errors(dpu_kms);
>
> @@ -3519,14 +3411,6 @@ static void dpu_crtc_install_properties(struct drm_crtc *crtc,
> "dram_ib", 0x0, 0, U64_MAX,
> catalog->perf.max_bw_high * 1000ULL,
> CRTC_PROP_DRAM_IB);
> - msm_property_install_range(&dpu_crtc->property_info,
> - "rot_prefill_bw", 0, 0, U64_MAX,
> - catalog->perf.max_bw_high * 1000ULL,
> - CRTC_PROP_ROT_PREFILL_BW);
> - msm_property_install_range(&dpu_crtc->property_info,
> - "rot_clk", 0, 0, U64_MAX,
> - dpu_kms->perf.max_core_clk_rate,
> - CRTC_PROP_ROT_CLK);
>
> msm_property_install_range(&dpu_crtc->property_info,
> "idle_timeout", IDLE_TIMEOUT, 0, U64_MAX, 0,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index 15e3eb6..9dec0b9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -201,8 +201,6 @@ struct dpu_crtc_event {
> * @misr_enable : boolean entry indicates misr enable/disable status.
> * @misr_frame_count : misr frame count provided by client
> * @misr_data : store misr data before turning off the clocks.
> - * @sbuf_flush_mask: flush mask for inline rotator
> - * @sbuf_flush_mask_old: inline rotator flush mask for previous commit
> * @power_event : registered power event handle
> * @cur_perf : current performance committed to clock/bandwidth driver
> * @rp_lock : serialization lock for resource pool
> @@ -265,9 +263,6 @@ struct dpu_crtc {
> u32 misr_frame_count;
> u32 misr_data[CRTC_DUAL_MIXERS];
>
> - u32 sbuf_flush_mask;
> - u32 sbuf_flush_mask_old;
> -
> struct dpu_power_event *power_event;
>
> struct dpu_core_perf_params cur_perf;
> @@ -290,12 +285,6 @@ struct dpu_crtc_res_ops {
> void (*put)(void *val);
> };
>
> -/* crtc resource type (0x0-0xffff reserved for hw block type */
> -#define DPU_CRTC_RES_ROT_OUT_FBO 0x10000
> -#define DPU_CRTC_RES_ROT_OUT_FB 0x10001
> -#define DPU_CRTC_RES_ROT_PLANE 0x10002
> -#define DPU_CRTC_RES_ROT_IN_FB 0x10003
> -
> #define DPU_CRTC_RES_FLAG_FREE BIT(0)
>
> /**
> @@ -357,8 +346,6 @@ struct dpu_crtc_respool {
> * @ds_dirty: Boolean to indicate if dirty or not
> * @ds_cfg: Destination scaler config
> * @new_perf: new performance state being requested
> - * @sbuf_cfg: stream buffer configuration
> - * @sbuf_prefill_line: number of line for inline rotator prefetch
> */
> struct dpu_crtc_state {
> struct drm_crtc_state base;
> @@ -384,9 +371,6 @@ struct dpu_crtc_state {
> struct dpu_hw_ds_cfg ds_cfg[DPU_MAX_DS_COUNT];
>
> struct dpu_core_perf_params new_perf;
> - struct dpu_ctl_sbuf_cfg sbuf_cfg;
> - u32 sbuf_prefill_line;
> -
> struct dpu_crtc_respool rp;
> };
>
> @@ -541,23 +525,6 @@ static inline bool dpu_crtc_is_enabled(struct drm_crtc *crtc)
> }
>
> /**
> - * dpu_crtc_get_inline_prefill - get current inline rotation prefill
> - * @crtc: Pointer to crtc
> - * return: number of prefill lines
> - */
> -static inline u32 dpu_crtc_get_inline_prefill(struct drm_crtc *crtc)
> -{
> - struct dpu_crtc_state *cstate;
> -
> - if (!crtc || !crtc->state)
> - return 0;
> -
> - cstate = to_dpu_crtc_state(crtc->state);
> - return cstate->sbuf_cfg.rot_op_mode != DPU_CTL_ROT_OP_MODE_OFFLINE ?
> - cstate->sbuf_prefill_line : 0;
> -}
> -
> -/**
> * dpu_crtc_event_queue - request event callback
> * @crtc: Pointer to drm crtc structure
> * @func: Pointer to callback function
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 91b9e07..d175286 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -1225,8 +1225,7 @@ static int _dpu_encoder_dsc_disable(struct dpu_encoder_virt *dpu_enc)
> }
>
> static int _dpu_encoder_update_rsc_client(
> - struct drm_encoder *drm_enc,
> - struct dpu_encoder_rsc_config *config, bool enable)
> + struct drm_encoder *drm_enc, bool enable)
> {
> struct dpu_encoder_virt *dpu_enc;
> struct drm_crtc *crtc;
> @@ -1265,13 +1264,11 @@ static int _dpu_encoder_update_rsc_client(
> (((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) &&
> disp_info->is_primary) ? DPU_RSC_CMD_STATE :
> DPU_RSC_VID_STATE) : DPU_RSC_IDLE_STATE;
> - prefill_lines = config ? mode_info->prefill_lines +
> - config->inline_rotate_prefill : mode_info->prefill_lines;
>
> /* compare specific items and reconfigure the rsc */
> if ((rsc_config->fps != mode_info->frame_rate) ||
> (rsc_config->vtotal != mode_info->vtotal) ||
> - (rsc_config->prefill_lines != prefill_lines) ||
> + (rsc_config->prefill_lines != mode_info->prefill_lines) ||
> (rsc_config->jitter_numer != mode_info->jitter_numer) ||
> (rsc_config->jitter_denom != mode_info->jitter_denom)) {
> rsc_config->fps = mode_info->frame_rate;
> @@ -1393,16 +1390,12 @@ static void _dpu_encoder_resource_control_rsc_update(
> struct drm_encoder *drm_enc, bool enable)
> {
> struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
> - struct dpu_encoder_rsc_config rsc_cfg = { 0 };
> int i;
>
> if (enable) {
> - rsc_cfg.inline_rotate_prefill =
> - dpu_crtc_get_inline_prefill(drm_enc->crtc);
> -
> - _dpu_encoder_update_rsc_client(drm_enc, &rsc_cfg, true);
> + _dpu_encoder_update_rsc_client(drm_enc, true);
> } else {
> - _dpu_encoder_update_rsc_client(drm_enc, NULL, false);
> + _dpu_encoder_update_rsc_client(drm_enc, false);
>
> /**
> * disable the vsync source after updating the rsc state. rsc
> @@ -1744,7 +1737,7 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
>
> _dpu_encoder_irq_control(drm_enc, true);
>
> - _dpu_encoder_update_rsc_client(drm_enc, NULL, true);
> + _dpu_encoder_update_rsc_client(drm_enc, true);
>
> DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
> DPU_ENC_RC_STATE_ON, DPU_EVTLOG_FUNC_CASE6);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> index 69fb26c..92b6832 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
> @@ -52,24 +52,14 @@ struct dpu_encoder_hw_resources {
>
> /**
> * dpu_encoder_kickoff_params - info encoder requires at kickoff
> - * @inline_rotate_prefill: number of lines to prefill for inline rotation
> * @affected_displays: bitmask, bit set means the ROI of the commit lies within
> * the bounds of the physical display at the bit index
> */
> struct dpu_encoder_kickoff_params {
> - u32 inline_rotate_prefill;
> unsigned long affected_displays;
> };
>
> /**
> - * dpu_encoder_rsc_config - rsc configuration for encoder
> - * @inline_rotate_prefill: number of lines to prefill for inline rotation
> - */
> -struct dpu_encoder_rsc_config {
> - u32 inline_rotate_prefill;
> -};
> -
> -/**
> * dpu_encoder_get_hw_resources - Populate table of required hardware resources
> * @encoder: encoder pointer
> * @hw_res: resource table to populate with encoder required resources
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index 3b05569..6c9b7d6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -290,15 +290,11 @@ static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys)
> * @base: Baseclass physical encoder structure
> * @hw_intf: Hardware interface to the intf registers
> * @timing_params: Current timing parameter
> - * @rot_fetch: Prefill for inline rotation
> - * @rot_fetch_valid: true if rot_fetch is updated (reset in enc enable)
> */
> struct dpu_encoder_phys_vid {
> struct dpu_encoder_phys base;
> struct dpu_hw_intf *hw_intf;
> struct intf_timing_params timing_params;
> - struct intf_prog_fetch rot_fetch;
> - bool rot_fetch_valid;
> };
>
> /**
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index 62c6f5c..1a88267 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -229,73 +229,6 @@ static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc,
> spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
> }
>
> -/*
> - * programmable_rot_fetch_config: Programs ROT to prefetch lines by offsetting
> - * the start of fetch into the vertical front porch for cases where the
> - * vsync pulse width and vertical back porch time is insufficient
> - *
> - * Gets # of lines to pre-fetch, then calculate VSYNC counter value.
> - * HW layer requires VSYNC counter of first pixel of tgt VFP line.
> - * @phys_enc: Pointer to physical encoder
> - * @rot_fetch_lines: number of line to prefill, or 0 to disable
> - */
> -static void programmable_rot_fetch_config(struct dpu_encoder_phys *phys_enc,
> - u32 rot_fetch_lines)
> -{
> - struct dpu_encoder_phys_vid *vid_enc =
> - to_dpu_encoder_phys_vid(phys_enc);
> - struct intf_prog_fetch f = { 0 };
> - struct intf_timing_params *timing;
> - u32 vfp_fetch_lines = 0;
> - u32 horiz_total = 0;
> - u32 vert_total = 0;
> - u32 rot_fetch_start_vsync_counter = 0;
> - u32 flush_mask = 0;
> - unsigned long lock_flags;
> -
> - if (!phys_enc || !vid_enc->hw_intf || !phys_enc->hw_ctl ||
> - !phys_enc->hw_ctl->ops.get_bitmask_intf ||
> - !phys_enc->hw_ctl->ops.update_pending_flush ||
> - !vid_enc->hw_intf->ops.setup_rot_start)
> - return;
> -
> - timing = &vid_enc->timing_params;
> - vfp_fetch_lines = programmable_fetch_get_num_lines(vid_enc, timing);
> - if (vfp_fetch_lines && rot_fetch_lines) {
> - vert_total = get_vertical_total(timing);
> - horiz_total = get_horizontal_total(timing);
> - if (vert_total >= (vfp_fetch_lines + rot_fetch_lines)) {
> - rot_fetch_start_vsync_counter =
> - (vert_total - vfp_fetch_lines - rot_fetch_lines) *
> - horiz_total + 1;
> - f.enable = 1;
> - f.fetch_start = rot_fetch_start_vsync_counter;
> - }
> - }
> -
> - /* return if rot_fetch does not change since last update */
> - if (vid_enc->rot_fetch_valid &&
> - !memcmp(&vid_enc->rot_fetch, &f, sizeof(f)))
> - return;
> -
> - DPU_DEBUG_VIDENC(vid_enc,
> - "rot_fetch_lines %u vfp_fetch_lines %u rot_fetch_start_vsync_counter %u\n",
> - rot_fetch_lines, vfp_fetch_lines,
> - rot_fetch_start_vsync_counter);
> -
> - phys_enc->hw_ctl->ops.get_bitmask_intf(
> - phys_enc->hw_ctl, &flush_mask, vid_enc->hw_intf->idx);
> - phys_enc->hw_ctl->ops.update_pending_flush(
> - phys_enc->hw_ctl, flush_mask);
> -
> - spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
> - vid_enc->hw_intf->ops.setup_rot_start(vid_enc->hw_intf, &f);
> - spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
> -
> - vid_enc->rot_fetch = f;
> - vid_enc->rot_fetch_valid = true;
> -}
> -
> static bool dpu_encoder_phys_vid_mode_fixup(
> struct dpu_encoder_phys *phys_enc,
> const struct drm_display_mode *mode,
> @@ -620,9 +553,6 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
> if (WARN_ON(!vid_enc->hw_intf->ops.enable_timing))
> return;
>
> - /* reset state variables until after first update */
> - vid_enc->rot_fetch_valid = false;
> -
> dpu_encoder_helper_split_config(phys_enc, vid_enc->hw_intf->idx);
>
> dpu_encoder_phys_vid_setup_timing_engine(phys_enc);
> @@ -759,8 +689,6 @@ static void dpu_encoder_phys_vid_prepare_for_kickoff(
> dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC);
> DPU_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic");
> }
> -
> - programmable_rot_fetch_config(phys_enc, params->inline_rotate_prefill);
> }
>
> static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 289b9ff..7019620 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -14,9 +14,6 @@
> #include <linux/slab.h>
> #include <linux/of_address.h>
> #include <linux/platform_device.h>
> -#if IS_ENABLED(CONFIG_DRM_MSM_ROTATOR)
> -#include <linux/soc/qcom/llcc-qcom.h>
> -#endif
> #include "dpu_hw_mdss.h"
> #include "dpu_hw_catalog.h"
> #include "dpu_hw_catalog_format.h"
> @@ -94,8 +91,6 @@
> */
> #define PROP_BITVALUE_ACCESS(p, i, j, k) ((p + i)->bit_value[j][k])
>
> -#define DEFAULT_SBUF_HEADROOM (20)
> -
> /*
> * Default parameter values
> */
> @@ -333,13 +328,6 @@ enum {
> REG_DMA_PROP_MAX
> };
>
> -enum {
> - INLINE_ROT_XIN,
> - INLINE_ROT_XIN_TYPE,
> - INLINE_ROT_CLK_CTRL,
> - INLINE_ROT_PROP_MAX
> -};
> -
> /*************************************************************
> * dts property definition
> *************************************************************/
> @@ -923,9 +911,6 @@ static void _dpu_sspp_setup_vig(struct dpu_mdss_cfg *dpu_cfg,
> "sspp_scaler%u", sspp->id - SSPP_VIG0);
> }
>
> - if (dpu_cfg->has_sbuf)
> - set_bit(DPU_SSPP_SBUF, &sspp->features);
> -
> sblk->csc_blk.id = DPU_SSPP_CSC;
> snprintf(sblk->csc_blk.name, DPU_HW_BLK_NAME_LEN,
> "sspp_csc%u", sspp->id - SSPP_VIG0);
> @@ -1295,8 +1280,6 @@ static int dpu_ctl_parse_dt(struct device_node *np,
> set_bit(DPU_CTL_SPLIT_DISPLAY, &ctl->features);
> if (i < MAX_PP_SPLIT_DISPLAY_CTL)
> set_bit(DPU_CTL_PINGPONG_SPLIT, &ctl->features);
> - if (dpu_cfg->has_sbuf)
> - set_bit(DPU_CTL_SBUF, &ctl->features);
> }
>
> end:
> @@ -1534,9 +1517,6 @@ static int dpu_intf_parse_dt(struct device_node *np,
> intf->controller_id = none_count;
> none_count++;
> }
> -
> - if (dpu_cfg->has_sbuf)
> - set_bit(DPU_INTF_ROT_START, &intf->features);
> }
>
> end:
> @@ -1761,170 +1741,6 @@ static void _dpu_dspp_setup_blocks(struct dpu_mdss_cfg *dpu_cfg,
> }
> }
>
> -#if IS_ENABLED(CONFIG_DRM_MSM_ROTATOR)
> -static struct dpu_prop_type inline_rot_prop[INLINE_ROT_PROP_MAX] = {
> - {INLINE_ROT_XIN, "qcom,dpu-inline-rot-xin", false,
> - PROP_TYPE_U32_ARRAY},
> - {INLINE_ROT_XIN_TYPE, "qcom,dpu-inline-rot-xin-type", false,
> - PROP_TYPE_STRING_ARRAY},
> - {INLINE_ROT_CLK_CTRL, "qcom,dpu-inline-rot-clk-ctrl", false,
> - PROP_TYPE_BIT_OFFSET_ARRAY},
> -};
> -
> -static void _dpu_inline_rot_parse_dt(struct device_node *np,
> - struct dpu_mdss_cfg *dpu_cfg, struct dpu_rot_cfg *rot)
> -{
> - int rc, prop_count[INLINE_ROT_PROP_MAX], i, j, index;
> - struct dpu_prop_value *prop_value = NULL;
> - bool prop_exists[INLINE_ROT_PROP_MAX];
> - u32 off_count, sspp_count = 0, wb_count = 0;
> - const char *type;
> -
> - prop_value = kcalloc(INLINE_ROT_PROP_MAX,
> - sizeof(struct dpu_prop_value), GFP_KERNEL);
> - if (!prop_value)
> - return;
> -
> - rc = _validate_dt_entry(np, inline_rot_prop,
> - ARRAY_SIZE(inline_rot_prop), prop_count, &off_count);
> - if (rc)
> - goto end;
> -
> - rc = _read_dt_entry(np, inline_rot_prop, ARRAY_SIZE(inline_rot_prop),
> - prop_count, prop_exists, prop_value);
> - if (rc)
> - goto end;
> -
> - for (i = 0; i < off_count; i++) {
> - rot->vbif_cfg[i].xin_id = PROP_VALUE_ACCESS(prop_value,
> - INLINE_ROT_XIN, i);
> - of_property_read_string_index(np,
> - inline_rot_prop[INLINE_ROT_XIN_TYPE].prop_name,
> - i, &type);
> -
> - if (!strcmp(type, "sspp")) {
> - rot->vbif_cfg[i].num = INLINE_ROT0_SSPP + sspp_count;
> - rot->vbif_cfg[i].is_read = true;
> - rot->vbif_cfg[i].clk_ctrl =
> - DPU_CLK_CTRL_INLINE_ROT0_SSPP
> - + sspp_count;
> - sspp_count++;
> - } else if (!strcmp(type, "wb")) {
> - rot->vbif_cfg[i].num = INLINE_ROT0_WB + wb_count;
> - rot->vbif_cfg[i].is_read = false;
> - rot->vbif_cfg[i].clk_ctrl =
> - DPU_CLK_CTRL_INLINE_ROT0_WB
> - + wb_count;
> - wb_count++;
> - } else {
> - DPU_ERROR("invalid rotator vbif type:%s\n", type);
> - goto end;
> - }
> -
> - index = rot->vbif_cfg[i].clk_ctrl;
> - if (index < 0 || index >= DPU_CLK_CTRL_MAX) {
> - DPU_ERROR("invalid clk_ctrl enum:%d\n", index);
> - goto end;
> - }
> -
> - for (j = 0; j < dpu_cfg->mdp_count; j++) {
> - dpu_cfg->mdp[j].clk_ctrls[index].reg_off =
> - PROP_BITVALUE_ACCESS(prop_value,
> - INLINE_ROT_CLK_CTRL, i, 0);
> - dpu_cfg->mdp[j].clk_ctrls[index].bit_off =
> - PROP_BITVALUE_ACCESS(prop_value,
> - INLINE_ROT_CLK_CTRL, i, 1);
> - }
> -
> - DPU_DEBUG("rot- xin:%d, num:%d, rd:%d, clk:%d:0x%x/%d\n",
> - rot->vbif_cfg[i].xin_id,
> - rot->vbif_cfg[i].num,
> - rot->vbif_cfg[i].is_read,
> - rot->vbif_cfg[i].clk_ctrl,
> - dpu_cfg->mdp[0].clk_ctrls[index].reg_off,
> - dpu_cfg->mdp[0].clk_ctrls[index].bit_off);
> - }
> -
> - rot->vbif_idx = VBIF_RT;
> - rot->xin_count = off_count;
> -
> -end:
> - kfree(prop_value);
> -}
> -#endif
> -
> -static int dpu_rot_parse_dt(struct device_node *np,
> - struct dpu_mdss_cfg *dpu_cfg)
> -{
> -#if IS_ENABLED(CONFIG_DRM_MSM_ROTATOR)
> - struct dpu_rot_cfg *rot;
> - struct platform_device *pdev;
> - struct of_phandle_args phargs;
> - struct llcc_slice_desc *slice;
> - int rc = 0, i;
> -
> - if (!dpu_cfg) {
> - DPU_ERROR("invalid argument\n");
> - rc = -EINVAL;
> - goto end;
> - }
> -
> - for (i = 0; i < ROT_MAX; i++) {
> - rot = dpu_cfg->rot + dpu_cfg->rot_count;
> - rot->base = 0;
> - rot->len = 0;
> -
> - rc = of_parse_phandle_with_args(np,
> - "qcom,dpu-inline-rotator", "#list-cells",
> - i, &phargs);
> - if (rc) {
> - rc = 0;
> - break;
> - } else if (!phargs.np || !phargs.args_count) {
> - rc = -EINVAL;
> - break;
> - }
> -
> - rot->id = ROT_0 + phargs.args[0];
> -
> - pdev = of_find_device_by_node(phargs.np);
> - if (pdev) {
> - slice = llcc_slice_getd(&pdev->dev, "rotator");
> - if (IS_ERR_OR_NULL(slice)) {
> - rot->pdev = NULL;
> - DPU_ERROR("failed to get system cache %ld\n",
> - PTR_ERR(slice));
> - } else {
> - rot->scid = llcc_get_slice_id(slice);
> - rot->slice_size = llcc_get_slice_size(slice);
> - rot->pdev = pdev;
> - llcc_slice_putd(slice);
> - DPU_DEBUG("rot:%d scid:%d slice_size:%zukb\n",
> - rot->id, rot->scid,
> - rot->slice_size);
> - _dpu_inline_rot_parse_dt(np, dpu_cfg, rot);
> - dpu_cfg->rot_count++;
> - }
> - } else {
> - rot->pdev = NULL;
> - DPU_ERROR("invalid dpu rotator node\n");
> - }
> -
> - of_node_put(phargs.np);
> - }
> -
> - if (dpu_cfg->rot_count) {
> - dpu_cfg->has_sbuf = true;
> - dpu_cfg->sbuf_headroom = DEFAULT_SBUF_HEADROOM;
> - }
> -
> -end:
> - return rc;
> -#else
> - return 0;
> -#endif
> -}
> -
> static int dpu_dspp_top_parse_dt(struct device_node *np,
> struct dpu_mdss_cfg *dpu_cfg)
> {
> @@ -3219,10 +3035,6 @@ struct dpu_mdss_cfg *dpu_hw_catalog_init(struct drm_device *dev, u32 hw_rev)
> if (rc)
> goto end;
>
> - rc = dpu_rot_parse_dt(np, dpu_cfg);
> - if (rc)
> - goto end;
> -
> rc = dpu_ctl_parse_dt(np, dpu_cfg);
> if (rc)
> goto end;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index aa5b256..402e929 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -119,7 +119,6 @@ enum {
> * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect
> * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support
> * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support
> - * @DPU_SSPP_SBUF, SSPP support inline stream buffer
> * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper
> * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec
> * @DPU_SSPP_CDP Supports client driven prefetch
> @@ -142,7 +141,6 @@ enum {
> DPU_SSPP_EXCL_RECT,
> DPU_SSPP_SMART_DMA_V1,
> DPU_SSPP_SMART_DMA_V2,
> - DPU_SSPP_SBUF,
> DPU_SSPP_TS_PREFILL,
> DPU_SSPP_TS_PREFILL_REC1,
> DPU_SSPP_CDP,
> @@ -219,27 +217,15 @@ enum {
> * CTL sub-blocks
> * @DPU_CTL_SPLIT_DISPLAY CTL supports video mode split display
> * @DPU_CTL_PINGPONG_SPLIT CTL supports pingpong split
> - * @DPU_CTL_SBUF CTL supports inline stream buffer
> * @DPU_CTL_MAX
> */
> enum {
> DPU_CTL_SPLIT_DISPLAY = 0x1,
> DPU_CTL_PINGPONG_SPLIT,
> - DPU_CTL_SBUF,
> DPU_CTL_MAX
> };
>
> /**
> - * INTF sub-blocks
> - * @DPU_INTF_ROT_START INTF supports rotator start trigger
> - * @DPU_INTF_MAX
> - */
> -enum {
> - DPU_INTF_ROT_START = 0x1,
> - DPU_INTF_MAX
> -};
> -
> -/**
> * WB sub-blocks and features
> * @DPU_WB_LINE_MODE Writeback module supports line/linear mode
> * @DPU_WB_BLOCK_MODE Writeback module supports block mode read
> @@ -710,44 +696,6 @@ struct dpu_wb_cfg {
> };
>
> /**
> - * struct dpu_rot_vbif_cfg - inline rotator vbif configs
> - * @xin_id xin client id
> - * @num enum identifying this block
> - * @is_read indicates read/write client
> - * @clk_ctrl index to clk control
> - */
> -struct dpu_rot_vbif_cfg {
> - u32 xin_id;
> - u32 num;
> - bool is_read;
> - enum dpu_clk_ctrl_type clk_ctrl;
> -};
> -
> -/**
> - * struct dpu_rot_cfg - information of rotator blocks
> - * @id enum identifying this block
> - * @base register offset of this block
> - * @len length of hardware block
> - * @features bit mask identifying sub-blocks/features
> - * @pdev private device handle
> - * @scid subcache identifier
> - * @slice_size subcache slice size
> - * @vbif_idx vbif identifier
> - * @xin_count number of xin clients
> - * @vbif_cfg vbif settings related to rotator
> - */
> -struct dpu_rot_cfg {
> - DPU_HW_BLK_INFO;
> - void *pdev;
> - int scid;
> - size_t slice_size;
> - u32 vbif_idx;
> -
> - u32 xin_count;
> - struct dpu_rot_vbif_cfg vbif_cfg[MAX_BLOCKS];
> -};
> -
> -/**
> * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting
> * @pps pixel per seconds
> * @ot_limit OT limit to use up to specified pixel per second
> @@ -909,8 +857,6 @@ struct dpu_perf_cfg {
> * @has_cdp Client driven prefetch feature status
> * @has_wb_ubwc UBWC feature supported on WB
> * @ubwc_version UBWC feature version (0x0 for not supported)
> - * @has_sbuf indicate if stream buffer is available
> - * @sbuf_headroom stream buffer headroom in lines
> * @has_idle_pc indicate if idle power collapse feature is supported
> * @dma_formats Supported formats for dma pipe
> * @cursor_formats Supported formats for cursor pipe
> @@ -934,8 +880,6 @@ struct dpu_mdss_cfg {
> bool has_dim_layer;
> bool has_wb_ubwc;
> u32 ubwc_version;
> - bool has_sbuf;
> - u32 sbuf_headroom;
> bool has_idle_pc;
> u32 vbif_qos_nlvl;
> u32 ts_prefill_rev;
> @@ -978,9 +922,6 @@ struct dpu_mdss_cfg {
> u32 wb_count;
> struct dpu_wb_cfg wb[MAX_BLOCKS];
>
> - u32 rot_count;
> - struct dpu_rot_cfg rot[MAX_BLOCKS];
> -
> u32 vbif_count;
> struct dpu_vbif_cfg vbif[MAX_BLOCKS];
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 44ef737..6922d8a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -31,12 +31,8 @@
> #define CTL_PREPARE 0x0d0
> #define CTL_SW_RESET 0x030
> #define CTL_LAYER_EXTN_OFFSET 0x40
> -#define CTL_ROT_TOP 0x0C0
> -#define CTL_ROT_FLUSH 0x0C4
> -#define CTL_ROT_START 0x0CC
>
> #define CTL_MIXER_BORDER_OUT BIT(24)
> -#define CTL_FLUSH_MASK_ROT BIT(27)
> #define CTL_FLUSH_MASK_CTL BIT(17)
>
> #define DPU_REG_RESET_TIMEOUT_US 2000
> @@ -87,16 +83,6 @@ static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx)
> DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);
> }
>
> -static inline void dpu_hw_ctl_trigger_rot_start(struct dpu_hw_ctl *ctx)
> -{
> - /* ROT flush bit is latched during ROT start, so set it first */
> - if (CTL_FLUSH_MASK_ROT & ctx->pending_flush_mask) {
> - ctx->pending_flush_mask &= ~CTL_FLUSH_MASK_ROT;
> - DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, CTL_FLUSH_MASK_ROT);
> - }
> - DPU_REG_WRITE(&ctx->hw, CTL_ROT_START, BIT(0));
> -}
> -
> static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx)
> {
> ctx->pending_flush_mask = 0x0;
> @@ -125,13 +111,6 @@ static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
> static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl *ctx)
> {
> struct dpu_hw_blk_reg_map *c = &ctx->hw;
> - u32 rot_op_mode;
> -
> - rot_op_mode = DPU_REG_READ(c, CTL_ROT_TOP) & 0x3;
> -
> - /* rotate flush bit is undefined if offline mode, so ignore it */
> - if (rot_op_mode == DPU_CTL_ROT_OP_MODE_OFFLINE)
> - return DPU_REG_READ(c, CTL_FLUSH) & ~CTL_FLUSH_MASK_ROT;
>
> return DPU_REG_READ(c, CTL_FLUSH);
> }
> @@ -293,19 +272,6 @@ static inline int dpu_hw_ctl_get_bitmask_wb(struct dpu_hw_ctl *ctx,
> return 0;
> }
>
> -static inline int dpu_hw_ctl_get_bitmask_rot(struct dpu_hw_ctl *ctx,
> - u32 *flushbits, enum dpu_rot rot)
> -{
> - switch (rot) {
> - case ROT_0:
> - *flushbits |= CTL_FLUSH_MASK_ROT;
> - break;
> - default:
> - return -EINVAL;
> - }
> - return 0;
> -}
> -
> static inline int dpu_hw_ctl_get_bitmask_cdm(struct dpu_hw_ctl *ctx,
> u32 *flushbits, enum dpu_cdm cdm)
> {
> @@ -552,17 +518,6 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
> DPU_REG_WRITE(c, CTL_TOP, intf_cfg);
> }
>
> -static void dpu_hw_ctl_setup_sbuf_cfg(struct dpu_hw_ctl *ctx,
> - struct dpu_ctl_sbuf_cfg *cfg)
> -{
> - struct dpu_hw_blk_reg_map *c = &ctx->hw;
> - u32 val;
> -
> - val = cfg->rot_op_mode & 0x3;
> -
> - DPU_REG_WRITE(c, CTL_ROT_TOP, val);
> -}
> -
> static void dpu_hw_reg_dma_flush(struct dpu_hw_ctl *ctx)
> {
> struct dpu_hw_reg_dma_ops *ops = dpu_reg_dma_get_ops();
> @@ -594,12 +549,6 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
> ops->get_bitmask_cdm = dpu_hw_ctl_get_bitmask_cdm;
> ops->get_bitmask_wb = dpu_hw_ctl_get_bitmask_wb;
> ops->reg_dma_flush = dpu_hw_reg_dma_flush;
> -
> - if (cap & BIT(DPU_CTL_SBUF)) {
> - ops->get_bitmask_rot = dpu_hw_ctl_get_bitmask_rot;
> - ops->setup_sbuf_cfg = dpu_hw_ctl_setup_sbuf_cfg;
> - ops->trigger_rot_start = dpu_hw_ctl_trigger_rot_start;
> - }
> };
>
> static struct dpu_hw_blk_ops dpu_hw_ops = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> index 47a6a0b..d3435be 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> @@ -29,20 +29,6 @@ enum dpu_ctl_mode_sel {
> DPU_CTL_MODE_SEL_CMD
> };
>
> -/**
> - * dpu_ctl_rot_op_mode - inline rotation mode
> - * DPU_CTL_ROT_OP_MODE_OFFLINE: offline rotation
> - * DPU_CTL_ROT_OP_MODE_RESERVED: reserved
> - * DPU_CTL_ROT_OP_MODE_INLINE_SYNC: inline rotation synchronous mode
> - * DPU_CTL_ROT_OP_MODE_INLINE_ASYNC: inline rotation asynchronous mode
> - */
> -enum dpu_ctl_rot_op_mode {
> - DPU_CTL_ROT_OP_MODE_OFFLINE,
> - DPU_CTL_ROT_OP_MODE_RESERVED,
> - DPU_CTL_ROT_OP_MODE_INLINE_SYNC,
> - DPU_CTL_ROT_OP_MODE_INLINE_ASYNC,
> -};
> -
> struct dpu_hw_ctl;
> /**
> * struct dpu_hw_stage_cfg - blending stage cfg
> @@ -72,14 +58,6 @@ struct dpu_hw_intf_cfg {
> };
>
> /**
> - * struct dpu_ctl_sbuf_cfg - control for stream buffer configuration
> - * @rot_op_mode: rotator operation mode
> - */
> -struct dpu_ctl_sbuf_cfg {
> - enum dpu_ctl_rot_op_mode rot_op_mode;
> -};
> -
> -/**
> * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions
> * Assumption is these functions will be called after clocks are enabled
> */
> @@ -100,13 +78,6 @@ struct dpu_hw_ctl_ops {
> void (*trigger_pending)(struct dpu_hw_ctl *ctx);
>
> /**
> - * kickoff rotator operation for Sw controlled interfaces
> - * DSI cmd mode and WB interface are SW controlled
> - * @ctx : ctl path ctx pointer
> - */
> - void (*trigger_rot_start)(struct dpu_hw_ctl *ctx);
> -
> - /**
> * Clear the value of the cached pending_flush_mask
> * No effect on hardware
> * @ctx : ctl path ctx pointer
> @@ -189,10 +160,6 @@ struct dpu_hw_ctl_ops {
> u32 *flushbits,
> enum dpu_wb blk);
>
> - int (*get_bitmask_rot)(struct dpu_hw_ctl *ctx,
> - u32 *flushbits,
> - enum dpu_rot blk);
> -
> /**
> * Set all blend stages to disabled
> * @ctx : ctl path ctx pointer
> @@ -208,9 +175,6 @@ struct dpu_hw_ctl_ops {
> void (*setup_blendstage)(struct dpu_hw_ctl *ctx,
> enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg);
>
> - void (*setup_sbuf_cfg)(struct dpu_hw_ctl *ctx,
> - struct dpu_ctl_sbuf_cfg *cfg);
> -
> /**
> * Flush the reg dma by sending last command.
> * @ctx : ctl path ctx pointer
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index 8302360..7386d46 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -230,25 +230,6 @@ static void dpu_hw_intf_setup_prg_fetch(
> DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable);
> }
>
> -static void dpu_hw_intf_setup_rot_start(
> - struct dpu_hw_intf *intf,
> - const struct intf_prog_fetch *fetch)
> -{
> - struct dpu_hw_blk_reg_map *c = &intf->hw;
> - int fetch_enable;
> -
> - fetch_enable = DPU_REG_READ(c, INTF_CONFIG);
> - if (fetch->enable) {
> - fetch_enable |= BIT(19);
> - DPU_REG_WRITE(c, INTF_PROG_ROT_START,
> - fetch->fetch_start);
> - } else {
> - fetch_enable &= ~BIT(19);
> - }
> -
> - DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable);
> -}
> -
> static void dpu_hw_intf_get_status(
> struct dpu_hw_intf *intf,
> struct intf_status *s)
> @@ -311,8 +292,6 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
> ops->setup_misr = dpu_hw_intf_setup_misr;
> ops->collect_misr = dpu_hw_intf_collect_misr;
> ops->get_line_count = dpu_hw_intf_get_line_count;
> - if (cap & BIT(DPU_INTF_ROT_START))
> - ops->setup_rot_start = dpu_hw_intf_setup_rot_start;
> }
>
> static struct dpu_hw_blk_ops dpu_hw_ops = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> index 9c54a19..a79d735 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> @@ -57,7 +57,6 @@ struct intf_status {
> * Assumption is these functions will be called after clocks are enabled
> * @ setup_timing_gen : programs the timing engine
> * @ setup_prog_fetch : enables/disables the programmable fetch logic
> - * @ setup_rot_start : enables/disables the rotator start trigger
> * @ enable_timing: enable/disable timing engine
> * @ get_status: returns if timing engine is enabled or not
> * @ setup_misr: enables/disables MISR in HW register
> @@ -72,9 +71,6 @@ struct dpu_hw_intf_ops {
> void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
> const struct intf_prog_fetch *fetch);
>
> - void (*setup_rot_start)(struct dpu_hw_intf *intf,
> - const struct intf_prog_fetch *fetch);
> -
> void (*enable_timing)(struct dpu_hw_intf *intf,
> u8 enable);
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> index 094a418..5ede2b5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> @@ -107,7 +107,6 @@ enum dpu_hw_blk_type {
> DPU_HW_BLK_INTF,
> DPU_HW_BLK_WB,
> DPU_HW_BLK_DSC,
> - DPU_HW_BLK_ROT,
> DPU_HW_BLK_MAX,
> };
>
> @@ -299,18 +298,6 @@ enum dpu_iommu_domain {
> DPU_IOMMU_DOMAIN_MAX
> };
>
> -enum dpu_rot {
> - ROT_0 = 1,
> - ROT_MAX
> -};
> -
> -enum dpu_inline_rot {
> - INLINE_ROT_NONE,
> - INLINE_ROT0_SSPP,
> - INLINE_ROT0_WB,
> - INLINE_ROT_MAX
> -};
> -
> /**
> * DPU HW,Component order color map
> */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.c
> deleted file mode 100644
> index b20a640..0000000
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.c
> +++ /dev/null
> @@ -1,961 +0,0 @@
> -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 and
> - * only version 2 as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - */
> -
> -#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
> -
> -#include <linux/mutex.h>
> -#include <linux/platform_device.h>
> -
> -#include "dpu_kms.h"
> -#include "dpu_hw_mdss.h"
> -#include "dpu_hwio.h"
> -#include "dpu_hw_catalog.h"
> -#include "dpu_hw_rot.h"
> -#include "dpu_formats.h"
> -#include "dpu_rotator_inline.h"
> -
> -#define DPU_MODIFLER(_modifier_) ((_modifier_) & 0x00ffffffffffffffULL)
> -#define DPU_MODIFIER_IS_TILE(_modifier_) \
> - DPU_MODIFLER((_modifier_) & DRM_FORMAT_MOD_QCOM_TILE)
> -#define DPU_MODIFIER_IS_UBWC(_modifier_) \
> - DPU_MODIFLER((_modifier_) & DRM_FORMAT_MOD_QCOM_COMPRESSED)
> -#define DPU_MODIFIER_IS_10B(_modifier_) \
> - DPU_MODIFLER((_modifier_) & DRM_FORMAT_MOD_QCOM_DX)
> -#define DPU_MODIFIER_IS_TIGHT(_modifier_) \
> - DPU_MODIFLER((_modifier_) & DRM_FORMAT_MOD_QCOM_TIGHT)
> -
> -/**
> - * _rot_offset - update register map of the given rotator instance
> - * @rot: rotator identifier
> - * @m: Pointer to mdss catalog
> - * @addr: i/o address mapping
> - * @b: Pointer to register block mapping structure
> - * return: Pointer to rotator configuration of the given instance
> - */
> -static struct dpu_rot_cfg *_rot_offset(enum dpu_rot rot,
> - struct dpu_mdss_cfg *m,
> - void __iomem *addr,
> - struct dpu_hw_blk_reg_map *b)
> -{
> - int i;
> -
> - for (i = 0; i < m->rot_count; i++) {
> - if (rot == m->rot[i].id) {
> - b->base_off = addr;
> - b->blk_off = m->rot[i].base;
> - b->hwversion = m->hwversion;
> - b->log_mask = DPU_DBG_MASK_ROT;
> - return &m->rot[i];
> - }
> - }
> -
> - return ERR_PTR(-EINVAL);
> -}
> -
> -/**
> - * _dpu_hw_rot_reg_dump - perform register dump
> - * @ptr: private pointer to rotator platform device
> - * return: None
> - */
> -static void _dpu_hw_rot_reg_dump(void *ptr)
> -{
> - dpu_rotator_inline_reg_dump((struct platform_device *) ptr);
> -}
> -
> -/**
> - * dpu_hw_rot_start - start rotator before any commit
> - * @hw: Pointer to rotator hardware driver
> - * return: 0 if success; error code otherwise
> - */
> -static int dpu_hw_rot_start(struct dpu_hw_rot *hw)
> -{
> - struct platform_device *pdev;
> - int rc;
> -
> - if (!hw || !hw->caps || !hw->caps->pdev) {
> - DPU_ERROR("invalid parameters\n");
> - return -EINVAL;
> - }
> -
> - pdev = hw->caps->pdev;
> -
> - rc = dpu_dbg_reg_register_cb(hw->name, _dpu_hw_rot_reg_dump, pdev);
> - if (rc)
> - DPU_ERROR("failed to register debug dump %d\n", rc);
> -
> - hw->rot_ctx = dpu_rotator_inline_open(pdev);
> - if (IS_ERR_OR_NULL(hw->rot_ctx)) {
> - rc = PTR_ERR(hw->rot_ctx);
> - hw->rot_ctx = NULL;
> - return rc;
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * dpu_hw_rot_stop - stop rotator after final commit
> - * @hw: Pointer to rotator hardware driver
> - * return: none
> - */
> -static void dpu_hw_rot_stop(struct dpu_hw_rot *hw)
> -{
> - if (!hw || !hw->caps || !hw->caps->pdev) {
> - DPU_ERROR("invalid parameter\n");
> - return;
> - }
> -
> - dpu_rotator_inline_release(hw->rot_ctx);
> - hw->rot_ctx = NULL;
> -
> - dpu_dbg_reg_unregister_cb(hw->name, _dpu_hw_rot_reg_dump,
> - hw->caps->pdev);
> -}
> -
> -/**
> - * dpu_hw_rot_to_v4l2_pixfmt - convert drm pixel format to v4l2 pixel format
> - * @drm_pixfmt: drm fourcc pixel format
> - * @drm_modifier: drm pixel format modifier
> - * @pixfmt: Pointer to v4l2 fourcc pixel format (output)
> - * return: 0 if success; error code otherwise
> - */
> -static int dpu_hw_rot_to_v4l2_pixfmt(u32 drm_pixfmt, u64 drm_modifier,
> - u32 *pixfmt)
> -{
> - u32 rc = 0;
> -
> - if (!pixfmt)
> - return -EINVAL;
> -
> - switch (drm_pixfmt) {
> - case DRM_FORMAT_BGR565:
> - if (DPU_MODIFIER_IS_UBWC(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_RGB_565_UBWC;
> - else
> - *pixfmt = DPU_PIX_FMT_RGB_565;
> - break;
> - case DRM_FORMAT_BGRA8888:
> - if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_ARGB_8888_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_ARGB_8888;
> - break;
> - case DRM_FORMAT_BGRX8888:
> - if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_XRGB_8888_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_XRGB_8888;
> - break;
> - case DRM_FORMAT_RGBA8888:
> - if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_ABGR_8888_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_ABGR_8888;
> - break;
> - case DRM_FORMAT_RGBX8888:
> - if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_XBGR_8888_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_XBGR_8888;
> - break;
> - case DRM_FORMAT_ABGR8888:
> - if (DPU_MODIFIER_IS_UBWC(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_RGBA_8888_UBWC;
> - else if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_RGBA_8888_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_RGBA_8888;
> - break;
> - case DRM_FORMAT_XBGR8888:
> - if (DPU_MODIFIER_IS_UBWC(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_RGBX_8888_UBWC;
> - else if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_RGBX_8888_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_RGBX_8888;
> - break;
> - case DRM_FORMAT_ARGB8888:
> - if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_BGRA_8888_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_BGRA_8888;
> - break;
> - case DRM_FORMAT_XRGB8888:
> - if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_BGRX_8888_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_BGRX_8888;
> - break;
> - case DRM_FORMAT_NV12:
> - if (DPU_MODIFIER_IS_UBWC(drm_modifier)) {
> - if (DPU_MODIFIER_IS_10B(drm_modifier)) {
> - if (DPU_MODIFIER_IS_TIGHT(drm_modifier))
> - *pixfmt =
> - DPU_PIX_FMT_Y_CBCR_H2V2_TP10_UBWC;
> - else
> - *pixfmt =
> - DPU_PIX_FMT_Y_CBCR_H2V2_P010_UBWC;
> - } else {
> - *pixfmt = DPU_PIX_FMT_Y_CBCR_H2V2_UBWC;
> - }
> - } else if (DPU_MODIFIER_IS_TILE(drm_modifier)) {
> - if (DPU_MODIFIER_IS_10B(drm_modifier)) {
> - if (DPU_MODIFIER_IS_TIGHT(drm_modifier))
> - *pixfmt =
> - DPU_PIX_FMT_Y_CBCR_H2V2_TP10;
> - else
> - *pixfmt =
> - DPU_PIX_FMT_Y_CBCR_H2V2_P010_TILE;
> - } else {
> - *pixfmt = DPU_PIX_FMT_Y_CBCR_H2V2_TILE;
> - }
> - } else {
> - if (DPU_MODIFIER_IS_10B(drm_modifier)) {
> - if (DPU_MODIFIER_IS_TIGHT(drm_modifier))
> - *pixfmt =
> - DPU_PIX_FMT_Y_CBCR_H2V2_TP10;
> - else
> - *pixfmt =
> - DPU_PIX_FMT_Y_CBCR_H2V2_P010;
> - } else {
> - *pixfmt = DPU_PIX_FMT_Y_CBCR_H2V2;
> - }
> - }
> - break;
> - case DRM_FORMAT_NV21:
> - if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_Y_CRCB_H2V2_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_Y_CRCB_H2V2;
> - break;
> - case DRM_FORMAT_BGRA1010102:
> - if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_ARGB_2101010_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_ARGB_2101010;
> - break;
> - case DRM_FORMAT_BGRX1010102:
> - if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_XRGB_2101010_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_XRGB_2101010;
> - break;
> - case DRM_FORMAT_RGBA1010102:
> - if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_ABGR_2101010_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_ABGR_2101010;
> - break;
> - case DRM_FORMAT_RGBX1010102:
> - if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_XBGR_2101010_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_XBGR_2101010;
> - break;
> - case DRM_FORMAT_ARGB2101010:
> - if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_BGRA_1010102_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_BGRA_1010102;
> - break;
> - case DRM_FORMAT_XRGB2101010:
> - if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_BGRX_1010102_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_BGRX_1010102;
> - break;
> - case DRM_FORMAT_ABGR2101010:
> - if (DPU_MODIFIER_IS_UBWC(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_RGBA_1010102_UBWC;
> - else if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_RGBA_1010102_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_RGBA_1010102;
> - break;
> - case DRM_FORMAT_XBGR2101010:
> - if (DPU_MODIFIER_IS_UBWC(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_RGBX_1010102_UBWC;
> - else if (DPU_MODIFIER_IS_TILE(drm_modifier))
> - *pixfmt = DPU_PIX_FMT_RGBX_1010102_TILE;
> - else
> - *pixfmt = DPU_PIX_FMT_RGBX_1010102;
> - break;
> - default:
> - DPU_ERROR("invalid drm pixel format %c%c%c%c/%llx\n",
> - drm_pixfmt >> 0, drm_pixfmt >> 8,
> - drm_pixfmt >> 16, drm_pixfmt >> 24,
> - drm_modifier);
> - rc = -EINVAL;
> - break;
> - }
> -
> - return rc;
> -}
> -
> -/**
> - * dpu_hw_rot_to_drm_pixfmt - convert v4l2 pixel format to drm pixel format
> - * @pixfmt: v4l2 fourcc pixel format
> - * @drm_pixfmt: Pointer to drm forucc pixel format (output)
> - * @drm_modifier: Pointer to drm pixel format modifier (output)
> - * return: 0 if success; error code otherwise
> - */
> -static int dpu_hw_rot_to_drm_pixfmt(u32 pixfmt, u32 *drm_pixfmt,
> - u64 *drm_modifier)
> -{
> - u32 rc = 0;
> -
> - switch (pixfmt) {
> - case DPU_PIX_FMT_RGB_565:
> - *drm_pixfmt = DRM_FORMAT_BGR565;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_RGB_565_UBWC:
> - *drm_pixfmt = DRM_FORMAT_BGR565;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_COMPRESSED |
> - DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_RGBA_8888:
> - *drm_pixfmt = DRM_FORMAT_ABGR8888;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_RGBX_8888:
> - *drm_pixfmt = DRM_FORMAT_XBGR8888;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_BGRA_8888:
> - *drm_pixfmt = DRM_FORMAT_ARGB8888;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_BGRX_8888:
> - *drm_pixfmt = DRM_FORMAT_XRGB8888;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_Y_CBCR_H2V2_UBWC:
> - *drm_pixfmt = DRM_FORMAT_NV12;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_COMPRESSED |
> - DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_Y_CRCB_H2V2:
> - *drm_pixfmt = DRM_FORMAT_NV21;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_RGBA_8888_UBWC:
> - *drm_pixfmt = DRM_FORMAT_ABGR8888;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_COMPRESSED |
> - DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_RGBX_8888_UBWC:
> - *drm_pixfmt = DRM_FORMAT_XBGR8888;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_COMPRESSED |
> - DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_Y_CBCR_H2V2:
> - *drm_pixfmt = DRM_FORMAT_NV12;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_ARGB_8888:
> - *drm_pixfmt = DRM_FORMAT_BGRA8888;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_XRGB_8888:
> - *drm_pixfmt = DRM_FORMAT_BGRX8888;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_ABGR_8888:
> - *drm_pixfmt = DRM_FORMAT_RGBA8888;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_XBGR_8888:
> - *drm_pixfmt = DRM_FORMAT_RGBX8888;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_ARGB_2101010:
> - *drm_pixfmt = DRM_FORMAT_BGRA1010102;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_XRGB_2101010:
> - *drm_pixfmt = DRM_FORMAT_BGRX1010102;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_ABGR_2101010:
> - *drm_pixfmt = DRM_FORMAT_RGBA1010102;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_XBGR_2101010:
> - *drm_pixfmt = DRM_FORMAT_RGBX1010102;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_BGRA_1010102:
> - *drm_pixfmt = DRM_FORMAT_ARGB2101010;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_BGRX_1010102:
> - *drm_pixfmt = DRM_FORMAT_XRGB2101010;
> - *drm_modifier = 0;
> - break;
> - case DPU_PIX_FMT_RGBA_8888_TILE:
> - *drm_pixfmt = DRM_FORMAT_ABGR8888;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_RGBX_8888_TILE:
> - *drm_pixfmt = DRM_FORMAT_XBGR8888;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_BGRA_8888_TILE:
> - *drm_pixfmt = DRM_FORMAT_ARGB8888;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_BGRX_8888_TILE:
> - *drm_pixfmt = DRM_FORMAT_XRGB8888;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_Y_CRCB_H2V2_TILE:
> - *drm_pixfmt = DRM_FORMAT_NV21;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_Y_CBCR_H2V2_TILE:
> - *drm_pixfmt = DRM_FORMAT_NV12;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_ARGB_8888_TILE:
> - *drm_pixfmt = DRM_FORMAT_BGRA8888;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_XRGB_8888_TILE:
> - *drm_pixfmt = DRM_FORMAT_BGRX8888;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_ABGR_8888_TILE:
> - *drm_pixfmt = DRM_FORMAT_RGBA8888;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_XBGR_8888_TILE:
> - *drm_pixfmt = DRM_FORMAT_RGBX8888;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_ARGB_2101010_TILE:
> - *drm_pixfmt = DRM_FORMAT_BGRA1010102;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_XRGB_2101010_TILE:
> - *drm_pixfmt = DRM_FORMAT_BGRX1010102;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_ABGR_2101010_TILE:
> - *drm_pixfmt = DRM_FORMAT_RGBA1010102;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_XBGR_2101010_TILE:
> - *drm_pixfmt = DRM_FORMAT_RGBX1010102;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_BGRA_1010102_TILE:
> - *drm_pixfmt = DRM_FORMAT_ARGB2101010;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_BGRX_1010102_TILE:
> - *drm_pixfmt = DRM_FORMAT_XRGB2101010;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_RGBA_1010102_UBWC:
> - *drm_pixfmt = DRM_FORMAT_ABGR2101010;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_COMPRESSED |
> - DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_RGBX_1010102_UBWC:
> - *drm_pixfmt = DRM_FORMAT_XBGR2101010;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_COMPRESSED |
> - DRM_FORMAT_MOD_QCOM_TILE;
> - break;
> - case DPU_PIX_FMT_Y_CBCR_H2V2_P010:
> - *drm_pixfmt = DRM_FORMAT_NV12;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_DX;
> - break;
> - case DPU_PIX_FMT_Y_CBCR_H2V2_P010_TILE:
> - *drm_pixfmt = DRM_FORMAT_NV12;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE |
> - DRM_FORMAT_MOD_QCOM_DX;
> - break;
> - case DPU_PIX_FMT_Y_CBCR_H2V2_P010_UBWC:
> - *drm_pixfmt = DRM_FORMAT_NV12;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_COMPRESSED |
> - DRM_FORMAT_MOD_QCOM_TILE |
> - DRM_FORMAT_MOD_QCOM_DX;
> - break;
> - case DPU_PIX_FMT_Y_CBCR_H2V2_TP10:
> - *drm_pixfmt = DRM_FORMAT_NV12;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_TILE |
> - DRM_FORMAT_MOD_QCOM_DX |
> - DRM_FORMAT_MOD_QCOM_TIGHT;
> - break;
> - case DPU_PIX_FMT_Y_CBCR_H2V2_TP10_UBWC:
> - *drm_pixfmt = DRM_FORMAT_NV12;
> - *drm_modifier = DRM_FORMAT_MOD_QCOM_COMPRESSED |
> - DRM_FORMAT_MOD_QCOM_TILE |
> - DRM_FORMAT_MOD_QCOM_DX |
> - DRM_FORMAT_MOD_QCOM_TIGHT;
> - break;
> - default:
> - DPU_DEBUG("invalid v4l2 pixel format %c%c%c%c\n",
> - pixfmt >> 0, pixfmt >> 8,
> - pixfmt >> 16, pixfmt >> 24);
> - rc = -EINVAL;
> - break;
> - }
> -
> - return rc;
> -}
> -
> -/**
> - * dpu_hw_rot_to_v4l2_buffer - convert drm buffer to v4l2 buffer
> - * @drm_pixfmt: pixel format in drm fourcc
> - * @drm_modifier: pixel format modifier
> - * @drm_addr: drm buffer address per plane
> - * @drm_len: drm buffer length per plane
> - * @drm_planes: drm buffer number of planes
> - * @v4l_addr: v4l2 buffer address per plane
> - * @v4l_len: v4l2 buffer length per plane
> - * @v4l_planes: v4l2 buffer number of planes
> - */
> -static void dpu_hw_rot_to_v4l2_buffer(u32 drm_pixfmt, u64 drm_modifier,
> - dma_addr_t *drm_addr, u32 *drm_len, u32 *drm_planes,
> - dma_addr_t *v4l_addr, u32 *v4l_len, u32 *v4l_planes)
> -{
> - int i, total_size = 0;
> -
> - for (i = 0; i < DPU_ROTATOR_INLINE_PLANE_MAX; i++) {
> - v4l_addr[i] = drm_addr[i];
> - v4l_len[i] = drm_len[i];
> - total_size += drm_len[i];
> - DPU_DEBUG("drm[%d]:%pad/%x\n", i, &drm_addr[i], drm_len[i]);
> - }
> -
> - if (DPU_MODIFIER_IS_UBWC(drm_modifier)) {
> - /* v4l2 driver uses plane[0] as single ubwc buffer plane */
> - v4l_addr[0] = drm_addr[2];
> - v4l_len[0] = total_size;
> - *v4l_planes = 1;
> - DPU_DEBUG("v4l2[0]:%pad/%x/%d\n", &v4l_addr[0], v4l_len[0],
> - *v4l_planes);
> - } else {
> - *v4l_planes = *drm_planes;
> - }
> -}
> -
> -/**
> - * dpu_hw_rot_commit - commit/execute given rotator command
> - * @hw: Pointer to rotator hardware driver
> - * @data: Pointer to command descriptor
> - * @hw_cmd: type of command to be executed
> - * return: 0 if success; error code otherwise
> - */
> -static int dpu_hw_rot_commit(struct dpu_hw_rot *hw, struct dpu_hw_rot_cmd *data,
> - enum dpu_hw_rot_cmd_type hw_cmd)
> -{
> - struct dpu_rotator_inline_cmd rot_cmd;
> - enum dpu_rotator_inline_cmd_type cmd_type;
> - void *priv_handle = NULL;
> - int rc;
> -
> - if (!hw || !data) {
> - DPU_ERROR("invalid parameter\n");
> - return -EINVAL;
> - }
> -
> - memset(&rot_cmd, 0, sizeof(struct dpu_rotator_inline_cmd));
> -
> - switch (hw_cmd) {
> - case DPU_HW_ROT_CMD_VALIDATE:
> - cmd_type = DPU_ROTATOR_INLINE_CMD_VALIDATE;
> - break;
> - case DPU_HW_ROT_CMD_COMMIT:
> - cmd_type = DPU_ROTATOR_INLINE_CMD_COMMIT;
> - break;
> - case DPU_HW_ROT_CMD_START:
> - cmd_type = DPU_ROTATOR_INLINE_CMD_START;
> - priv_handle = data->priv_handle;
> - break;
> - case DPU_HW_ROT_CMD_CLEANUP:
> - cmd_type = DPU_ROTATOR_INLINE_CMD_CLEANUP;
> - priv_handle = data->priv_handle;
> - break;
> - default:
> - DPU_ERROR("invalid hw rotator command %d\n", hw_cmd);
> - return -EINVAL;
> - }
> -
> - rot_cmd.sequence_id = data->sequence_id;
> - rot_cmd.video_mode = data->video_mode;
> - rot_cmd.fps = data->fps;
> -
> - /*
> - * DRM rotation property is specified in counter clockwise direction
> - * whereas rotator h/w rotates in clockwise direction.
> - * Convert rotation property to clockwise 90 by toggling h/v flip
> - */
> - rot_cmd.rot90 = data->rot90;
> - rot_cmd.hflip = data->rot90 ? !data->hflip : data->hflip;
> - rot_cmd.vflip = data->rot90 ? !data->vflip : data->vflip;
> -
> - rot_cmd.clkrate = data->clkrate;
> - rot_cmd.data_bw = 0;
> - rot_cmd.prefill_bw = data->prefill_bw;
> - rot_cmd.src_width = data->src_width;
> - rot_cmd.src_height = data->src_height;
> - rot_cmd.src_rect_x = data->src_rect_x;
> - rot_cmd.src_rect_y = data->src_rect_y;
> - rot_cmd.src_rect_w = data->src_rect_w;
> - rot_cmd.src_rect_h = data->src_rect_h;
> - rot_cmd.dst_writeback = data->dst_writeback;
> - rot_cmd.dst_rect_x = data->dst_rect_x;
> - rot_cmd.dst_rect_y = data->dst_rect_y;
> - rot_cmd.dst_rect_w = data->dst_rect_w;
> - rot_cmd.dst_rect_h = data->dst_rect_h;
> - rot_cmd.priv_handle = priv_handle;
> -
> - rc = dpu_hw_rot_to_v4l2_pixfmt(data->src_pixel_format,
> - data->src_modifier, &rot_cmd.src_pixfmt);
> - if (rc) {
> - DPU_ERROR("invalid src format %d\n", rc);
> - return rc;
> - }
> -
> - /* calculate preferred output format during validation */
> - if (hw_cmd == DPU_HW_ROT_CMD_VALIDATE) {
> - rc = dpu_rotator_inline_get_dst_pixfmt(hw->caps->pdev,
> - rot_cmd.src_pixfmt, &rot_cmd.dst_pixfmt);
> - if (rc) {
> - DPU_ERROR("invalid src format %d\n", rc);
> - return rc;
> - }
> -
> - rc = dpu_hw_rot_to_drm_pixfmt(rot_cmd.dst_pixfmt,
> - &data->dst_pixel_format, &data->dst_modifier);
> - if (rc) {
> - DPU_ERROR("invalid dst format %c%c%c%c\n",
> - rot_cmd.dst_pixfmt >> 0,
> - rot_cmd.dst_pixfmt >> 8,
> - rot_cmd.dst_pixfmt >> 16,
> - rot_cmd.dst_pixfmt >> 24);
> - return rc;
> - }
> -
> - data->dst_format = dpu_get_dpu_format_ext(
> - data->dst_pixel_format, data->dst_modifier);
> - if (!data->dst_format) {
> - DPU_ERROR("failed to get dst format\n");
> - return -EINVAL;
> - }
> - } else {
> - rc = dpu_hw_rot_to_v4l2_pixfmt(data->dst_pixel_format,
> - data->dst_modifier, &rot_cmd.dst_pixfmt);
> - if (rc) {
> - DPU_ERROR("invalid dst format %d\n", rc);
> - return rc;
> - }
> -
> - dpu_hw_rot_to_v4l2_buffer(data->src_pixel_format,
> - data->src_modifier,
> - data->src_iova, data->src_len,
> - &data->src_planes,
> - rot_cmd.src_addr, rot_cmd.src_len,
> - &rot_cmd.src_planes);
> -
> - dpu_hw_rot_to_v4l2_buffer(data->dst_pixel_format,
> - data->dst_modifier,
> - data->dst_iova, data->dst_len,
> - &data->dst_planes,
> - rot_cmd.dst_addr, rot_cmd.dst_len,
> - &rot_cmd.dst_planes);
> - }
> -
> - /* only process any command if client is master or for validation */
> - if (data->master || hw_cmd == DPU_HW_ROT_CMD_VALIDATE) {
> - DPU_DEBUG("dispatch seq:%d cmd:%d\n", data->sequence_id,
> - hw_cmd);
> -
> - rc = dpu_rotator_inline_commit(hw->rot_ctx, &rot_cmd, cmd_type);
> - if (rc)
> - return rc;
> -
> - /* return to caller */
> - data->priv_handle = rot_cmd.priv_handle;
> - } else {
> - DPU_DEBUG("bypass seq:%d cmd:%d\n", data->sequence_id, hw_cmd);
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * dpu_hw_rot_get_format_caps - get pixel format capability
> - * @hw: Pointer to rotator hardware driver
> - * return: Pointer to pixel format capability array: NULL otherwise
> - */
> -static const struct dpu_format_extended *dpu_hw_rot_get_format_caps(
> - struct dpu_hw_rot *hw)
> -{
> - int rc, i, j, len;
> - u32 *v4l_pixfmts;
> - struct dpu_format_extended *drm_pixfmts;
> - struct platform_device *pdev;
> -
> - if (!hw || !hw->caps || !hw->caps->pdev) {
> - DPU_ERROR("invalid rotator hw\n");
> - return NULL;
> - }
> -
> - pdev = hw->caps->pdev;
> -
> - if (hw->format_caps)
> - return hw->format_caps;
> -
> - len = dpu_rotator_inline_get_pixfmt_caps(pdev, true, NULL, 0);
> - if (len < 0) {
> - DPU_ERROR("invalid pixfmt caps %d\n", len);
> - return NULL;
> - }
> -
> - v4l_pixfmts = kcalloc(len, sizeof(u32), GFP_KERNEL);
> - if (!v4l_pixfmts)
> - goto done;
> -
> - dpu_rotator_inline_get_pixfmt_caps(pdev, true, v4l_pixfmts, len);
> -
> - /* allocate one more to indicate termination */
> - drm_pixfmts = kzalloc((len + 1) * sizeof(struct dpu_format_extended),
> - GFP_KERNEL);
> - if (!drm_pixfmts)
> - goto done;
> -
> - for (i = 0, j = 0; i < len; i++) {
> - rc = dpu_hw_rot_to_drm_pixfmt(v4l_pixfmts[i],
> - &drm_pixfmts[j].fourcc_format,
> - &drm_pixfmts[j].modifier);
> - if (!rc) {
> - DPU_DEBUG("%d: vl42:%c%c%c%c => drm:%c%c%c%c/0x%llx\n",
> - i, v4l_pixfmts[i] >> 0, v4l_pixfmts[i] >> 8,
> - v4l_pixfmts[i] >> 16, v4l_pixfmts[i] >> 24,
> - drm_pixfmts[j].fourcc_format >> 0,
> - drm_pixfmts[j].fourcc_format >> 8,
> - drm_pixfmts[j].fourcc_format >> 16,
> - drm_pixfmts[j].fourcc_format >> 24,
> - drm_pixfmts[j].modifier);
> - j++;
> - } else {
> - DPU_DEBUG("%d: vl42:%c%c%c%c not mapped\n",
> - i, v4l_pixfmts[i] >> 0, v4l_pixfmts[i] >> 8,
> - v4l_pixfmts[i] >> 16, v4l_pixfmts[i] >> 24);
> - }
> - }
> -
> - hw->format_caps = drm_pixfmts;
> -done:
> - kfree(v4l_pixfmts);
> -
> - return hw->format_caps;
> -}
> -
> -/**
> - * dpu_hw_rot_get_downscale_caps - get scaling capability string
> - * @hw: Pointer to rotator hardware driver
> - * return: Pointer to capability string: NULL otherwise
> - */
> -static const char *dpu_hw_rot_get_downscale_caps(struct dpu_hw_rot *hw)
> -{
> - int len;
> - struct platform_device *pdev;
> -
> - if (!hw || !hw->caps || !hw->caps->pdev) {
> - DPU_ERROR("invalid rotator hw\n");
> - return NULL;
> - }
> -
> - pdev = hw->caps->pdev;
> -
> - if (hw->downscale_caps)
> - return hw->downscale_caps;
> -
> - len = dpu_rotator_inline_get_downscale_caps(pdev, NULL, 0);
> - if (len < 0) {
> - DPU_ERROR("invalid scaling caps %d\n", len);
> - return NULL;
> - }
> -
> - /* add one for ending zero */
> - len += 1;
> - hw->downscale_caps = kzalloc(len, GFP_KERNEL);
> - dpu_rotator_inline_get_downscale_caps(pdev, hw->downscale_caps, len);
> -
> - return hw->downscale_caps;
> -}
> -
> -/**
> - * dpu_hw_rot_get_cache_size - get cache size
> - * @hw: Pointer to rotator hardware driver
> - * return: size of cache
> - */
> -static size_t dpu_hw_rot_get_cache_size(struct dpu_hw_rot *hw)
> -{
> - if (!hw || !hw->caps) {
> - DPU_ERROR("invalid rotator hw\n");
> - return 0;
> - }
> -
> - return hw->caps->slice_size;
> -}
> -
> -/**
> - * dpu_hw_rot_get_maxlinewidth - get maximum line width of rotator
> - * @hw: Pointer to rotator hardware driver
> - * return: maximum line width
> - */
> -static int dpu_hw_rot_get_maxlinewidth(struct dpu_hw_rot *hw)
> -{
> - struct platform_device *pdev;
> -
> - if (!hw || !hw->caps || !hw->caps->pdev) {
> - DPU_ERROR("invalid rotator hw\n");
> - return 0;
> - }
> -
> - pdev = hw->caps->pdev;
> -
> - return dpu_rotator_inline_get_maxlinewidth(pdev);
> -}
> -
> -/**
> - * _setup_rot_ops - setup rotator operations
> - * @ops: Pointer to operation table
> - * @features: available feature bitmask
> - * return: none
> - */
> -static void _setup_rot_ops(struct dpu_hw_rot_ops *ops, unsigned long features)
> -{
> - ops->commit = dpu_hw_rot_commit;
> - ops->get_format_caps = dpu_hw_rot_get_format_caps;
> - ops->get_downscale_caps = dpu_hw_rot_get_downscale_caps;
> - ops->get_cache_size = dpu_hw_rot_get_cache_size;
> - ops->get_maxlinewidth = dpu_hw_rot_get_maxlinewidth;
> -}
> -
> -/**
> - * dpu_hw_rot_blk_stop - stop rotator block
> - * @hw_blk: Pointer to base hardware block
> - * return: none
> - */
> -static void dpu_hw_rot_blk_stop(struct dpu_hw_blk *hw_blk)
> -{
> - struct dpu_hw_rot *hw_rot = to_dpu_hw_rot(hw_blk);
> -
> - DPU_DEBUG("type:%d id:%d\n", hw_blk->type, hw_blk->id);
> -
> - dpu_hw_rot_stop(hw_rot);
> -}
> -
> -/**
> - * dpu_hw_rot_blk_start - art rotator block
> - * @hw_blk: Pointer to base hardware block
> - * return: 0 if success; error code otherwise
> - */
> -static int dpu_hw_rot_blk_start(struct dpu_hw_blk *hw_blk)
> -{
> - struct dpu_hw_rot *hw_rot = to_dpu_hw_rot(hw_blk);
> - int rc = 0;
> -
> - DPU_DEBUG("type:%d id:%d\n", hw_blk->type, hw_blk->id);
> -
> - rc = dpu_hw_rot_start(hw_rot);
> -
> - return rc;
> -}
> -
> -static struct dpu_hw_blk_ops dpu_hw_rot_ops = {
> - .start = dpu_hw_rot_blk_start,
> - .stop = dpu_hw_rot_blk_stop,
> -};
> -
> -/**
> - * dpu_hw_rot_init - create/initialize given rotator instance
> - * @idx: index of given rotator
> - * @addr: i/o address mapping
> - * @m: Pointer to mdss catalog
> - * return: Pointer to hardware rotator driver of the given instance
> - */
> -struct dpu_hw_rot *dpu_hw_rot_init(enum dpu_rot idx,
> - void __iomem *addr,
> - struct dpu_mdss_cfg *m)
> -{
> - struct dpu_hw_rot *c;
> - struct dpu_rot_cfg *cfg;
> - int rc;
> -
> - c = kzalloc(sizeof(*c), GFP_KERNEL);
> - if (!c)
> - return ERR_PTR(-ENOMEM);
> -
> - cfg = _rot_offset(idx, m, addr, &c->hw);
> - if (IS_ERR(cfg)) {
> - WARN(1, "Unable to find rot idx=%d\n", idx);
> - kfree(c);
> - return ERR_PTR(-EINVAL);
> - }
> -
> - /* Assign ops */
> - c->idx = idx;
> - c->caps = cfg;
> - _setup_rot_ops(&c->ops, c->caps->features);
> - snprintf(c->name, ARRAY_SIZE(c->name), "dpu_rot_%d", idx - ROT_0);
> -
> - rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_ROT, idx, &dpu_hw_rot_ops);
> - if (rc) {
> - DPU_ERROR("failed to init hw blk %d\n", rc);
> - goto blk_init_error;
> - }
> -
> - return c;
> -
> -blk_init_error:
> - kzfree(c);
> -
> - return ERR_PTR(rc);
> -}
> -
> -/**
> - * dpu_hw_rot_destroy - destroy given hardware rotator driver
> - * @hw_rot: Pointer to hardware rotator driver
> - * return: none
> - */
> -void dpu_hw_rot_destroy(struct dpu_hw_rot *hw_rot)
> -{
> - if (hw_rot) {
> - dpu_hw_blk_destroy(&hw_rot->base);
> - kfree(hw_rot->downscale_caps);
> - kfree(hw_rot->format_caps);
> - }
> - kfree(hw_rot);
> -}
> -
> -struct dpu_hw_rot *dpu_hw_rot_get(struct dpu_hw_rot *hw_rot)
> -{
> - struct dpu_hw_blk *hw_blk = dpu_hw_blk_get(hw_rot ? &hw_rot->base :
> - NULL, DPU_HW_BLK_ROT, -1);
> -
> - return IS_ERR_OR_NULL(hw_blk) ? NULL : to_dpu_hw_rot(hw_blk);
> -}
> -
> -void dpu_hw_rot_put(struct dpu_hw_rot *hw_rot)
> -{
> - struct dpu_hw_blk *hw_blk = hw_rot ? &hw_rot->base : NULL;
> -
> - dpu_hw_blk_put(hw_blk);
> -}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.h
> deleted file mode 100644
> index df15ed5..0000000
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_rot.h
> +++ /dev/null
> @@ -1,190 +0,0 @@
> -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 and
> - * only version 2 as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - */
> -
> -#ifndef _DPU_HW_ROT_H
> -#define _DPU_HW_ROT_H
> -
> -#include "dpu_hw_catalog.h"
> -#include "dpu_hw_mdss.h"
> -#include "dpu_hw_util.h"
> -#include "dpu_hw_blk.h"
> -
> -#define DPU_HW_ROT_NAME_SIZE 80
> -
> -struct dpu_hw_rot;
> -
> -/**
> - * enum dpu_hw_rot_cmd_type - type of rotator hardware command
> - * @DPU_HW_ROT_CMD_VALDIATE: validate rotator command; do not commit
> - * @DPU_HW_ROT_CMD_COMMIT: commit/execute rotator command
> - * @DPU_HW_ROT_CMD_START: mdp is ready to start
> - * @DPU_HW_ROT_CMD_CLEANUP: cleanup rotator command after it is done
> - */
> -enum dpu_hw_rot_cmd_type {
> - DPU_HW_ROT_CMD_VALIDATE,
> - DPU_HW_ROT_CMD_COMMIT,
> - DPU_HW_ROT_CMD_START,
> - DPU_HW_ROT_CMD_CLEANUP,
> -};
> -
> -/**
> - * struct dpu_hw_rot_cmd - definition of hardware rotation command
> - * @master: true if client is the master in source split inline rotation
> - * @sequence_id: command sequence identifier
> - * @fps: frame rate of the stream in frame per second
> - * @rot90: true if rotation 90 in counter clockwise is required
> - * @hflip: true if horizontal flip is required prior to rotation
> - * @vflip: true if vertical flip is required prior to rotation
> - * @video_mode: true if rotator is feeding into video interface
> - * @clkrate : clock rate in Hz
> - * @prefill_bw: prefill bandwidth in Bps (video mode only)
> - * @src_iova: source i/o virtual address
> - * @src_len: source i/o buffer length
> - * @src_planes: source plane number
> - * @src_format: pointer to source dpu pixel format
> - * @src_pixel_format: source pixel format in drm fourcc
> - * @src_modifier: source pixel format modifier
> - * @src_width: source width in pixel
> - * @src_height: source height in pixel
> - * @src_rect_x: source rectangle x coordinate
> - * @src_rect_y: source rectangle y coordinate
> - * @src_rect_w: source rectangle width
> - * @src_rect_h: source rectangle height
> - * @dst_writeback: true if writeback of rotated output is required
> - * @dst_iova: destination i/o virtual address
> - * @dst_len: destination i/o buffer length
> - * @dst_planes: destination plane number
> - * @dst_format: pointer to destination dpu pixel format (input/output)
> - * @dst_pixel_format: destination pixel format in drm fourcc (input/output)
> - * @dst_modifier: destination pixel format modifier (input/output)
> - * @dst_rect_x: destination rectangle x coordinate
> - * @dst_rect_y: destination rectangle y coordinate
> - * @dst_rect_w: destination rectangle width
> - * @dst_rect_h: destination rectangle height
> - * @priv_handle: private handle of rotator driver (output)
> - */
> -struct dpu_hw_rot_cmd {
> - bool master;
> - u32 sequence_id;
> - u32 fps;
> - bool rot90;
> - bool hflip;
> - bool vflip;
> - bool video_mode;
> - u64 clkrate;
> - u64 prefill_bw;
> - dma_addr_t src_iova[4];
> - u32 src_len[4];
> - u32 src_planes;
> - const struct dpu_format *src_format;
> - u32 src_pixel_format;
> - u64 src_modifier;
> - u32 src_width;
> - u32 src_height;
> - u32 src_stride;
> - u32 src_rect_x;
> - u32 src_rect_y;
> - u32 src_rect_w;
> - u32 src_rect_h;
> - bool dst_writeback;
> - dma_addr_t dst_iova[4];
> - u32 dst_len[4];
> - u32 dst_planes;
> - const struct dpu_format *dst_format;
> - u32 dst_pixel_format;
> - u64 dst_modifier;
> - u32 dst_rect_x;
> - u32 dst_rect_y;
> - u32 dst_rect_w;
> - u32 dst_rect_h;
> - void *priv_handle;
> -};
> -
> -/**
> - * struct dpu_hw_rot_ops - interface to the rotator hw driver functions
> - * Assumption is these functions will be called after clocks are enabled
> - */
> -struct dpu_hw_rot_ops {
> - int (*commit)(struct dpu_hw_rot *hw, struct dpu_hw_rot_cmd *data,
> - enum dpu_hw_rot_cmd_type cmd);
> - const struct dpu_format_extended *(*get_format_caps)(
> - struct dpu_hw_rot *hw);
> - const char *(*get_downscale_caps)(struct dpu_hw_rot *hw);
> - size_t (*get_cache_size)(struct dpu_hw_rot *hw);
> - int (*get_maxlinewidth)(struct dpu_hw_rot *hw);
> -};
> -
> -/**
> - * struct dpu_hw_rot : ROT driver object
> - * @base: hw block base object
> - * @hw: hardware address map
> - * @idx: instance index
> - * @caps: capabilities bitmask
> - * @ops: operation table
> - * @rot_ctx: pointer to private rotator context
> - * @format_caps: pointer to pixel format capability array
> - * @downscale_caps: pointer to scaling capability string
> - */
> -struct dpu_hw_rot {
> - struct dpu_hw_blk base;
> - struct dpu_hw_blk_reg_map hw;
> - char name[DPU_HW_ROT_NAME_SIZE];
> - int idx;
> - const struct dpu_rot_cfg *caps;
> - struct dpu_hw_rot_ops ops;
> - void *rot_ctx;
> - struct dpu_format_extended *format_caps;
> - char *downscale_caps;
> -};
> -
> -/**
> - * dpu_hw_rot_init - initialize and return rotator hw driver object.
> - * @idx: wb_path index for which driver object is required
> - * @addr: mapped register io address of MDP
> - * @m : pointer to mdss catalog data
> - */
> -struct dpu_hw_rot *dpu_hw_rot_init(enum dpu_rot idx,
> - void __iomem *addr,
> - struct dpu_mdss_cfg *m);
> -
> -/**
> - * dpu_hw_rot_destroy - destroy rotator hw driver object.
> - * @hw_rot: Pointer to rotator hw driver object
> - */
> -void dpu_hw_rot_destroy(struct dpu_hw_rot *hw_rot);
> -
> -/**
> - * to_dpu_hw_rot - convert base object dpu_hw_base to rotator object
> - * @hw: Pointer to base hardware block
> - * return: Pointer to rotator hardware block
> - */
> -static inline struct dpu_hw_rot *to_dpu_hw_rot(struct dpu_hw_blk *hw)
> -{
> - return container_of(hw, struct dpu_hw_rot, base);
> -}
> -
> -/**
> - * dpu_hw_rot_get - get next available hardware rotator, or increment reference
> - * count if hardware rotator provided
> - * @hw_rot: Pointer to hardware rotator
> - * return: Pointer to rotator hardware block if success; NULL otherwise
> - */
> -struct dpu_hw_rot *dpu_hw_rot_get(struct dpu_hw_rot *hw_rot);
> -
> -/**
> - * dpu_hw_rot_put - put the given hardware rotator
> - * @hw_rot: Pointer to hardware rotator
> - * return: none
> - */
> -void dpu_hw_rot_put(struct dpu_hw_rot *hw_rot);
> -
> -#endif /*_DPU_HW_ROT_H */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 3fecf33..5343184 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -102,11 +102,6 @@
> #define SSPP_QOS_CTRL_CREQ_VBLANK_MASK 0x3
> #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF 20
>
> -#define SSPP_SYS_CACHE_MODE 0x1BC
> -#define SSPP_SBUF_STATUS_PLANE0 0x1C0
> -#define SSPP_SBUF_STATUS_PLANE1 0x1C4
> -#define SSPP_SBUF_STATUS_PLANE_EMPTY BIT(16)
> -
> /* DPU_SSPP_SCALER_QSEED2 */
> #define SCALE_CONFIG 0x04
> #define COMP0_3_PHASE_STEP_X 0x10
> @@ -759,45 +754,6 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx,
> DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl);
> }
>
> -static void dpu_hw_sspp_setup_sys_cache(struct dpu_hw_pipe *ctx,
> - struct dpu_hw_pipe_sc_cfg *cfg)
> -{
> - u32 idx, val;
> -
> - if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
> - return;
> -
> - if (!cfg)
> - return;
> -
> - val = ((cfg->op_mode & 0x3) << 18) |
> - ((cfg->rd_en & 0x1) << 15) |
> - ((cfg->rd_scid & 0x1f) << 8) |
> - ((cfg->rd_noallocate & 0x1) << 4) |
> - ((cfg->rd_op_type & 0xf) << 0);
> -
> - DPU_REG_WRITE(&ctx->hw, SSPP_SYS_CACHE_MODE + idx, val);
> -}
> -
> -static void dpu_hw_sspp_get_sbuf_status(struct dpu_hw_pipe *ctx,
> - struct dpu_hw_pipe_sbuf_status *status)
> -{
> - u32 idx, val;
> -
> - if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx))
> - return;
> -
> - if (!status)
> - return;
> -
> - val = DPU_REG_READ(&ctx->hw, SSPP_SBUF_STATUS_PLANE0 + idx);
> - status->empty[0] = val & SSPP_SBUF_STATUS_PLANE_EMPTY ? true : false;
> - status->rd_ptr[0] = val & 0xffff;
> - val = DPU_REG_READ(&ctx->hw, SSPP_SBUF_STATUS_PLANE1 + idx);
> - status->empty[1] = val & SSPP_SBUF_STATUS_PLANE_EMPTY ? true : false;
> - status->rd_ptr[1] = val & 0xffff;
> -}
> -
> static void dpu_hw_sspp_setup_ts_prefill(struct dpu_hw_pipe *ctx,
> struct dpu_hw_pipe_ts_cfg *cfg,
> enum dpu_sspp_multirect_index index)
> @@ -931,11 +887,6 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c,
> dpu_setup_pipe_pa_memcol_v1_7;
> }
>
> - if (test_bit(DPU_SSPP_SBUF, &features)) {
> - c->ops.setup_sys_cache = dpu_hw_sspp_setup_sys_cache;
> - c->ops.get_sbuf_status = dpu_hw_sspp_get_sbuf_status;
> - }
> -
> if (test_bit(DPU_SSPP_CDP, &features))
> c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index de971f1..a32ecc6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -224,41 +224,6 @@ struct dpu_hw_pipe_cdp_cfg {
> };
>
> /**
> - * enum system cache rotation operation mode
> - */
> -enum {
> - DPU_PIPE_SC_OP_MODE_OFFLINE,
> - DPU_PIPE_SC_OP_MODE_INLINE_SINGLE,
> - DPU_PIPE_SC_OP_MODE_INLINE_LEFT,
> - DPU_PIPE_SC_OP_MODE_INLINE_RIGHT,
> -};
> -
> -/**
> - * enum system cache read operation type
> - */
> -enum {
> - DPU_PIPE_SC_RD_OP_TYPE_CACHEABLE,
> - DPU_PIPE_SC_RD_OP_TYPE_INVALIDATE,
> - DPU_PIPE_SC_RD_OP_TYPE_EVICTION,
> -};
> -
> -/**
> - * struct dpu_hw_pipe_sc_cfg - system cache configuration
> - * @op_mode: rotation operating mode
> - * @rd_en: system cache read enable
> - * @rd_scid: system cache read block id
> - * @rd_noallocate: system cache read no allocate attribute
> - * @rd_op_type: system cache read operation type
> - */
> -struct dpu_hw_pipe_sc_cfg {
> - u32 op_mode;
> - bool rd_en;
> - u32 rd_scid;
> - bool rd_noallocate;
> - u32 rd_op_type;
> -};
> -
> -/**
> * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
> * @size: size to prefill in bytes, or zero to disable
> * @time: time to prefill in usec, or zero to disable
> @@ -269,21 +234,6 @@ struct dpu_hw_pipe_ts_cfg {
> };
>
> /**
> - * Maximum number of stream buffer plane
> - */
> -#define DPU_PIPE_SBUF_PLANE_NUM 2
> -
> -/**
> - * struct dpu_hw_pipe_sbuf_status - stream buffer status
> - * @empty: indicate if stream buffer is empty of not
> - * @rd_ptr: current read pointer of stream buffer
> - */
> -struct dpu_hw_pipe_sbuf_status {
> - bool empty[DPU_PIPE_SBUF_PLANE_NUM];
> - u32 rd_ptr[DPU_PIPE_SBUF_PLANE_NUM];
> -};
> -
> -/**
> * struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions
> * Caller must call the init function to get the pipe context for each pipe
> * Assumption is these functions will be called after clocks are enabled
> @@ -472,22 +422,6 @@ struct dpu_hw_sspp_ops {
> u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx);
>
> /**
> - * setup_sys_cache - setup system cache configuration
> - * @ctx: Pointer to pipe context
> - * @cfg: Pointer to system cache configuration
> - */
> - void (*setup_sys_cache)(struct dpu_hw_pipe *ctx,
> - struct dpu_hw_pipe_sc_cfg *cfg);
> -
> - /**
> - * get_sbuf_status - get stream buffer status
> - * @ctx: Pointer to pipe context
> - * @status: Pointer to stream buffer status
> - */
> - void (*get_sbuf_status)(struct dpu_hw_pipe *ctx,
> - struct dpu_hw_pipe_sbuf_status *status);
> -
> - /**
> * setup_ts_prefill - setup prefill traffic shaper
> * @ctx: Pointer to pipe context
> * @cfg: Pointer to traffic shaper configuration
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 9e9c9d2..2d1f265 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -36,7 +36,6 @@
> #include "dpu_vbif.h"
> #include "dpu_plane.h"
> #include "dpu_color_processing.h"
> -#include "dpu_hw_rot.h"
>
> static bool suspend_blank = true;
> module_param(suspend_blank, bool, 0400);
> @@ -100,10 +99,7 @@ enum dpu_plane_qos {
> * @csc_ptr: Points to dpu_csc_cfg structure to use for current
> * @mplane_list: List of multirect planes of the same pipe
> * @catalog: Points to dpu catalog structure
> - * @sbuf_mode: force stream buffer mode if set
> - * @sbuf_writeback: force stream buffer writeback if set
> * @revalidate: force revalidation of all the plane properties
> - * @blob_rot_caps: Pointer to rotator capability blob
> */
> struct dpu_plane {
> struct drm_plane base;
> @@ -125,8 +121,6 @@ struct dpu_plane {
> bool is_virtual;
> struct list_head mplane_list;
> struct dpu_mdss_cfg *catalog;
> - u32 sbuf_mode;
> - u32 sbuf_writeback;
> bool revalidate;
>
> struct dpu_csc_cfg csc_cfg;
> @@ -140,7 +134,6 @@ struct dpu_plane {
> struct msm_property_info property_info;
> struct msm_property_data property_data[PLANE_PROP_COUNT];
> struct drm_property_blob *blob_info;
> - struct drm_property_blob *blob_rot_caps;
>
> /* debugfs related stuff */
> struct dentry *debugfs_root;
> @@ -164,27 +157,6 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
> return to_dpu_kms(priv->kms);
> }
>
> -/**
> - * _dpu_plane_get_crtc_state - obtain crtc state attached to given plane state
> - * @pstate: Pointer to drm plane state
> - * return: Pointer to crtc state if success; pointer error, otherwise
> - */
> -static struct drm_crtc_state *_dpu_plane_get_crtc_state(
> - struct drm_plane_state *pstate)
> -{
> - struct drm_crtc_state *cstate;
> -
> - if (!pstate || !pstate->crtc)
> - return NULL;
> -
> - if (pstate->state)
> - cstate = drm_atomic_get_crtc_state(pstate->state, pstate->crtc);
> - else
> - cstate = pstate->crtc->state;
> -
> - return cstate;
> -}
> -
> static bool dpu_plane_enabled(struct drm_plane_state *state)
> {
> return state && state->fb && state->crtc;
> @@ -192,19 +164,7 @@ static bool dpu_plane_enabled(struct drm_plane_state *state)
>
> static bool dpu_plane_sspp_enabled(struct drm_plane_state *state)
> {
> - return state && to_dpu_plane_state(state)->rot.out_fb && state->crtc;
> -}
> -
> -/**
> - * dpu_plane_crtc_enabled - determine if crtc of given plane state is enabled
> - * @state: Pointer to drm plane state
> - * return: true if plane and the associated crtc are both enabled
> - */
> -static bool dpu_plane_crtc_enabled(struct drm_plane_state *state)
> -{
> - return dpu_plane_enabled(state) && state->crtc->state &&
> - state->crtc->state->active &&
> - state->crtc->state->enable;
> + return state && state->crtc;
> }
>
> /**
> @@ -219,10 +179,8 @@ static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane,
> {
> struct dpu_plane *pdpu, *tmp;
> struct dpu_plane_state *pstate;
> - struct dpu_plane_rot_state *rstate;
> u32 fixed_buff_size;
> u32 total_fl;
> - u32 hflip_bytes;
>
> if (!plane || !fmt || !plane->state || !src_width || !fmt->bpp) {
> DPU_ERROR("invalid arguments\n");
> @@ -231,7 +189,6 @@ static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane,
>
> pdpu = to_dpu_plane(plane);
> pstate = to_dpu_plane_state(plane->state);
> - rstate = &pstate->rot;
> fixed_buff_size = pdpu->pipe_sblk->pixel_ram_size;
>
> list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) {
> @@ -243,36 +200,30 @@ static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane,
> src_width = max_t(u32, src_width, tmp->pipe_cfg.src_rect.w);
> }
>
> - if ((rstate->out_rotation & DRM_MODE_REFLECT_X) &&
> - DPU_FORMAT_IS_LINEAR(fmt))
> - hflip_bytes = (src_width + 32) * fmt->bpp;
> - else
> - hflip_bytes = 0;
> -
> if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
> if (fmt->chroma_sample == DPU_CHROMA_420) {
> /* NV12 */
> - total_fl = (fixed_buff_size / 2 - hflip_bytes) /
> + total_fl = (fixed_buff_size / 2) /
> ((src_width + 32) * fmt->bpp);
> } else {
> /* non NV12 */
> - total_fl = (fixed_buff_size / 2 - hflip_bytes) * 2 /
> + total_fl = (fixed_buff_size / 2) * 2 /
> ((src_width + 32) * fmt->bpp);
> }
> } else {
> if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
> - total_fl = (fixed_buff_size / 2 - hflip_bytes) * 2 /
> + total_fl = (fixed_buff_size / 2) * 2 /
> ((src_width + 32) * fmt->bpp);
> } else {
> - total_fl = (fixed_buff_size - hflip_bytes) * 2 /
> + total_fl = (fixed_buff_size) * 2 /
> ((src_width + 32) * fmt->bpp);
> }
> }
>
> - DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u hf:%d fl:%u\n",
> + DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n",
> plane->base.id, pdpu->pipe - SSPP_VIG0,
> (char *)&fmt->base.pixel_format,
> - src_width, hflip_bytes, total_fl);
> + src_width, total_fl);
>
> return total_fl;
> }
> @@ -696,90 +647,6 @@ static void _dpu_plane_set_input_fence(struct dpu_plane *pdpu,
> DPU_DEBUG_PLANE(pdpu, "0x%llX\n", fd);
> }
>
> -/**
> - * _dpu_plane_inline_rot_set_ot_limit - set OT limit for the given inline
> - * rotation xin client
> - * @plane: pointer to drm plane
> - * @crtc: pointer to drm crtc
> - * @cfg: pointer to rotator vbif config
> - * @rect_w: rotator frame width
> - * @rect_h: rotator frame height
> - */
> -static void _dpu_plane_inline_rot_set_ot_limit(struct drm_plane *plane,
> - struct drm_crtc *crtc, const struct dpu_rot_vbif_cfg *cfg,
> - u32 rect_w, u32 rect_h)
> -{
> - struct dpu_vbif_set_ot_params ot_params;
> - struct msm_drm_private *priv;
> - struct dpu_kms *dpu_kms;
> -
> - if (!plane || !plane->dev) {
> - DPU_ERROR("invalid arguments\n");
> - return;
> - }
> -
> - priv = plane->dev->dev_private;
> - if (!priv || !priv->kms) {
> - DPU_ERROR("invalid KMS reference\n");
> - return;
> - }
> -
> - dpu_kms = to_dpu_kms(priv->kms);
> -
> - memset(&ot_params, 0, sizeof(ot_params));
> - ot_params.xin_id = cfg->xin_id;
> - ot_params.num = cfg->num;
> - ot_params.width = rect_w;
> - ot_params.height = rect_h;
> - ot_params.is_wfd = false;
> - ot_params.frame_rate = crtc->mode.vrefresh;
> - ot_params.vbif_idx = VBIF_RT;
> - ot_params.clk_ctrl = cfg->clk_ctrl;
> - ot_params.rd = cfg->is_read;
> -
> - dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
> -}
> -
> -/**
> - * _dpu_plane_inline_rot_set_qos_remap - set vbif QoS for the given inline
> - * rotation xin client
> - * @plane: Pointer to drm plane
> - * @cfg: Pointer to rotator vbif cfg
> - */
> -static void _dpu_plane_inline_rot_set_qos_remap(struct drm_plane *plane,
> - const struct dpu_rot_vbif_cfg *cfg)
> -{
> - struct dpu_vbif_set_qos_params qos_params;
> - struct msm_drm_private *priv;
> - struct dpu_kms *dpu_kms;
> -
> - if (!plane || !plane->dev) {
> - DPU_ERROR("invalid arguments\n");
> - return;
> - }
> -
> - priv = plane->dev->dev_private;
> - if (!priv || !priv->kms) {
> - DPU_ERROR("invalid KMS reference\n");
> - return;
> - }
> -
> - dpu_kms = to_dpu_kms(priv->kms);
> -
> - memset(&qos_params, 0, sizeof(qos_params));
> - qos_params.vbif_idx = VBIF_RT;
> - qos_params.xin_id = cfg->xin_id;
> - qos_params.clk_ctrl = cfg->clk_ctrl;
> - qos_params.num = cfg->num;
> - qos_params.is_rt = true;
> -
> - DPU_DEBUG("vbif:%d xin:%d num:%d rt:%d clk_ctrl:%d\n",
> - qos_params.vbif_idx, qos_params.xin_id,
> - qos_params.num, qos_params.is_rt, qos_params.clk_ctrl);
> -
> - dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
> -}
> -
> int dpu_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
> {
> struct dpu_plane *pdpu;
> @@ -847,7 +714,6 @@ static int _dpu_plane_get_aspace(
> struct msm_gem_address_space **aspace)
> {
> struct dpu_kms *kms;
> - int mode;
>
> if (!pdpu || !pstate || !aspace) {
> DPU_ERROR("invalid parameters\n");
> @@ -1456,1102 +1322,6 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu,
> return 0;
> }
>
> -/**
> - * _dpu_plane_fb_get/put - framebuffer callback for crtc res ops
> - */
> -static void *_dpu_plane_fb_get(void *fb, u32 type, u64 tag)
> -{
> - drm_framebuffer_get(fb);
> - return fb;
> -}
> -static void _dpu_plane_fb_put(void *fb)
> -{
> - drm_framebuffer_put(fb);
> -}
> -static struct dpu_crtc_res_ops fb_res_ops = {
> - .put = _dpu_plane_fb_put,
> - .get = _dpu_plane_fb_get,
> -};
> -
> -/**
> - * _dpu_plane_fbo_get/put - framebuffer object callback for crtc res ops
> - */
> -static void *_dpu_plane_fbo_get(void *fbo, u32 type, u64 tag)
> -{
> - dpu_kms_fbo_reference(fbo);
> - return fbo;
> -}
> -static void _dpu_plane_fbo_put(void *fbo)
> -{
> - dpu_kms_fbo_unreference(fbo);
> -}
> -static struct dpu_crtc_res_ops fbo_res_ops = {
> - .put = _dpu_plane_fbo_put,
> - .get = _dpu_plane_fbo_get,
> -};
> -
> -/**
> - * dpu_plane_rot_calc_prefill - calculate rotator start prefill
> - * @plane: Pointer to drm plane
> - * return: prefill time in line
> - */
> -u32 dpu_plane_rot_calc_prefill(struct drm_plane *plane)
> -{
> - struct drm_plane_state *state;
> - struct dpu_plane_state *pstate;
> - struct dpu_plane_rot_state *rstate;
> - struct dpu_kms *dpu_kms;
> - u32 blocksize = 128;
> - u32 prefill_line = 0;
> -
> - if (!plane || !plane->state || !plane->state->fb) {
> - DPU_ERROR("invalid parameters\n");
> - return 0;
> - }
> -
> - dpu_kms = _dpu_plane_get_kms(plane);
> - state = plane->state;
> - pstate = to_dpu_plane_state(state);
> - rstate = &pstate->rot;
> -
> - if (!dpu_kms || !dpu_kms->catalog) {
> - DPU_ERROR("invalid kms\n");
> - return 0;
> - }
> -
> - if (rstate->out_fb_format)
> - dpu_format_get_block_size(rstate->out_fb_format,
> - &blocksize, &blocksize);
> -
> - prefill_line = blocksize + dpu_kms->catalog->sbuf_headroom;
> - prefill_line = mult_frac(prefill_line, rstate->out_src_h >> 16,
> - state->crtc_h);
> - DPU_DEBUG(
> - "plane%d.%d blk:%u head:%u vdst/vsrc:%u/%u prefill:%u\n",
> - plane->base.id, rstate->sequence_id,
> - blocksize, dpu_kms->catalog->sbuf_headroom,
> - state->crtc_h, rstate->out_src_h >> 16,
> - prefill_line);
> -
> - return prefill_line;
> -}
> -
> -/**
> - * dpu_plane_rot_calc_cfg - calculate rotator/sspp configuration by
> - * enumerating over all planes attached to the same rotator
> - * @plane: Pointer to drm plane
> - * @state: Pointer to drm state to be updated
> - * return: 0 if success; error code otherwise
> - */
> -static int dpu_plane_rot_calc_cfg(struct drm_plane *plane,
> - struct drm_plane_state *state)
> -{
> - struct dpu_plane_state *pstate;
> - struct dpu_plane_rot_state *rstate;
> - struct drm_crtc_state *cstate;
> - struct drm_rect *in_rot, *out_rot;
> - struct drm_plane *attached_plane;
> - u32 dst_x, dst_y, dst_w, dst_h;
> - int found = 0;
> - int xpos = 0;
> - int ret;
> -
> - if (!plane || !state || !state->state) {
> - DPU_ERROR("invalid parameters\n");
> - return -EINVAL;
> - }
> -
> - cstate = _dpu_plane_get_crtc_state(state);
> - if (IS_ERR_OR_NULL(cstate)) {
> - ret = PTR_ERR(cstate);
> - DPU_ERROR("invalid crtc state %d\n", ret);
> - return ret;
> - }
> -
> - pstate = to_dpu_plane_state(state);
> - rstate = &pstate->rot;
> -
> - in_rot = &rstate->in_rot_rect;
> - *in_rot = drm_plane_state_src(state);
> -
> - out_rot = &rstate->out_rot_rect;
> - dst_x = dpu_plane_get_property(pstate, PLANE_PROP_ROT_DST_X);
> - dst_y = dpu_plane_get_property(pstate, PLANE_PROP_ROT_DST_Y);
> - dst_w = dpu_plane_get_property(pstate, PLANE_PROP_ROT_DST_W);
> - dst_h = dpu_plane_get_property(pstate, PLANE_PROP_ROT_DST_H);
> -
> - if (!dst_w && !dst_h) {
> - rstate->out_rot_rect = rstate->in_rot_rect;
> - drm_rect_rotate(&rstate->out_rot_rect, state->fb->width << 16,
> - state->fb->height << 16, rstate->in_rotation);
> - } else {
> - out_rot->x1 = dst_x;
> - out_rot->y1 = dst_y;
> - out_rot->x2 = dst_x + dst_w;
> - out_rot->y2 = dst_y + dst_h;
> - }
> -
> - rstate->out_src_rect = rstate->out_rot_rect;
> -
> - /* enumerating over all planes attached to the same rotator */
> - drm_atomic_crtc_state_for_each_plane(attached_plane, cstate) {
> - struct drm_plane_state *attached_state;
> - struct dpu_plane_state *attached_pstate;
> - struct dpu_plane_rot_state *attached_rstate;
> - struct drm_rect attached_out_rect;
> -
> - attached_state = drm_atomic_get_existing_plane_state(
> - state->state, attached_plane);
> -
> - if (!attached_state)
> - continue;
> -
> - attached_pstate = to_dpu_plane_state(attached_state);
> - attached_rstate = &attached_pstate->rot;
> -
> - if (attached_state->fb != state->fb)
> - continue;
> -
> - if (dpu_plane_get_property(pstate, PLANE_PROP_ROTATION) !=
> - dpu_plane_get_property(attached_pstate,
> - PLANE_PROP_ROTATION))
> - continue;
> -
> - found++;
> -
> - /* skip itself */
> - if (attached_plane == plane)
> - continue;
> -
> - /* find bounding rotator source roi */
> - if (attached_state->src_x < in_rot->x1)
> - in_rot->x1 = attached_state->src_x;
> -
> - if (attached_state->src_y < in_rot->y1)
> - in_rot->y1 = attached_state->src_y;
> -
> - if (attached_state->src_x + attached_state->src_w > in_rot->x2)
> - in_rot->x2 = attached_state->src_x +
> - attached_state->src_w;
> -
> - if (attached_state->src_y + attached_state->src_h > in_rot->y2)
> - in_rot->y2 = attached_state->src_y +
> - attached_state->src_h;
> -
> - /* find bounding rotator destination roi */
> - dst_x = dpu_plane_get_property(attached_pstate,
> - PLANE_PROP_ROT_DST_X);
> - dst_y = dpu_plane_get_property(attached_pstate,
> - PLANE_PROP_ROT_DST_Y);
> - dst_w = dpu_plane_get_property(attached_pstate,
> - PLANE_PROP_ROT_DST_W);
> - dst_h = dpu_plane_get_property(attached_pstate,
> - PLANE_PROP_ROT_DST_H);
> - if (!dst_w && !dst_h) {
> - attached_out_rect = drm_plane_state_src(attached_state);
> - drm_rect_rotate(&attached_out_rect,
> - state->fb->width << 16,
> - state->fb->height << 16,
> - rstate->in_rotation);
> - } else {
> - attached_out_rect.x1 = dst_x;
> - attached_out_rect.y1 = dst_y;
> - attached_out_rect.x2 = dst_x + dst_w;
> - attached_out_rect.y2 = dst_y + dst_h;
> - }
> -
> - /* check source split left/right mismatch */
> - if (attached_out_rect.y1 != rstate->out_src_rect.y1 ||
> - attached_out_rect.y2 != rstate->out_src_rect.y2) {
> - DPU_ERROR(
> - "plane%d.%u src:%dx%d+%d+%d rot:0x%llx fb:%d plane%d.%u src:%dx%d+%d+%d rot:0x%llx fb:%d mismatch\n",
> - plane->base.id,
> - rstate->sequence_id,
> - state->src_w >> 16,
> - state->src_h >> 16,
> - state->src_x >> 16,
> - state->src_y >> 16,
> - dpu_plane_get_property(pstate,
> - PLANE_PROP_ROTATION),
> - state->fb ?
> - state->fb->base.id :
> - -1,
> - attached_plane->base.id,
> - attached_rstate->sequence_id,
> - attached_state->src_w >> 16,
> - attached_state->src_h >> 16,
> - attached_state->src_x >> 16,
> - attached_state->src_y >> 16,
> - dpu_plane_get_property(attached_pstate,
> - PLANE_PROP_ROTATION),
> - attached_state->fb ?
> - attached_state->fb->base.id :
> - -1);
> - DPU_ERROR(
> - "plane%d.%u sspp:%dx%d+%d+%d plane%d.%u sspp:%dx%d+%d+%d\n",
> - plane->base.id,
> - rstate->sequence_id,
> - (rstate->out_src_rect.x2 -
> - rstate->out_src_rect.x1) >> 16,
> - (rstate->out_src_rect.y2 -
> - rstate->out_src_rect.y1) >> 16,
> - rstate->out_src_rect.x1 >> 16,
> - rstate->out_src_rect.y1 >> 16,
> - attached_plane->base.id,
> - attached_rstate->sequence_id,
> - (attached_out_rect.x2 -
> - attached_out_rect.x1) >> 16,
> - (attached_out_rect.y2 -
> - attached_out_rect.y1) >> 16,
> - attached_out_rect.x1 >> 16,
> - attached_out_rect.y1 >> 16);
> - DPU_EVT32(DRMID(plane),
> - rstate->sequence_id,
> - rstate->out_src_rect.x1 >> 16,
> - rstate->out_src_rect.y1 >> 16,
> - (rstate->out_src_rect.x2 -
> - rstate->out_src_rect.x1) >> 16,
> - (rstate->out_src_rect.y2 -
> - rstate->out_src_rect.y1) >> 16,
> - attached_plane->base.id,
> - attached_rstate->sequence_id,
> - attached_out_rect.x1 >> 16,
> - attached_out_rect.y1 >> 16,
> - (attached_out_rect.x2 -
> - attached_out_rect.x1) >> 16,
> - (attached_out_rect.y2 -
> - attached_out_rect.y1) >> 16,
> - DPU_EVTLOG_ERROR);
> - return -EINVAL;
> - }
> -
> - /* find relative sspp position */
> - if (attached_out_rect.x1 < rstate->out_src_rect.x1)
> - xpos++;
> -
> - if (attached_out_rect.x1 < out_rot->x1)
> - out_rot->x1 = attached_out_rect.x1;
> -
> - if (attached_out_rect.y1 < out_rot->y1)
> - out_rot->y1 = attached_out_rect.y1;
> -
> - if (attached_out_rect.x2 > out_rot->x2)
> - out_rot->x2 = attached_out_rect.x2;
> -
> - if (attached_out_rect.y2 > out_rot->y2)
> - out_rot->y2 = attached_out_rect.y2;
> -
> - DPU_DEBUG("plane%d.%u src_x:%d sspp:%dx%d+%d+%d/%dx%d+%d+%d\n",
> - attached_plane->base.id,
> - attached_rstate->sequence_id,
> - attached_rstate->out_src_rect.x1 >> 16,
> - attached_state->src_w >> 16,
> - attached_state->src_h >> 16,
> - attached_state->src_x >> 16,
> - attached_state->src_y >> 16,
> - drm_rect_width(&attached_rstate->out_src_rect) >> 16,
> - drm_rect_height(&attached_rstate->out_src_rect) >> 16,
> - attached_rstate->out_src_rect.x1 >> 16,
> - attached_rstate->out_src_rect.y1 >> 16);
> - }
> -
> - rstate->out_xpos = xpos;
> - rstate->nplane = found;
> -
> - DPU_DEBUG("plane%d.%u xpos:%d/%d rot:%dx%d+%d+%d/%dx%d+%d+%d\n",
> - plane->base.id, rstate->sequence_id,
> - rstate->out_xpos, rstate->nplane,
> - drm_rect_width(in_rot) >> 16,
> - drm_rect_height(in_rot) >> 16,
> - in_rot->x1 >> 16, in_rot->y1 >> 16,
> - drm_rect_width(&rstate->out_rot_rect) >> 16,
> - drm_rect_height(&rstate->out_rot_rect) >> 16,
> - rstate->out_rot_rect.x1 >> 16,
> - rstate->out_rot_rect.y1 >> 16);
> - DPU_EVT32(DRMID(plane), rstate->sequence_id,
> - rstate->out_xpos, rstate->nplane,
> - in_rot->x1 >> 16, in_rot->y1 >> 16,
> - drm_rect_width(in_rot) >> 16,
> - drm_rect_height(in_rot) >> 16,
> - rstate->out_rot_rect.x1 >> 16,
> - rstate->out_rot_rect.y1 >> 16,
> - drm_rect_width(&rstate->out_rot_rect) >> 16,
> - drm_rect_height(&rstate->out_rot_rect) >> 16);
> -
> - return 0;
> -}
> -
> -/**
> - * dpu_plane_rot_submit_command - commit given state for the rotator stage
> - * @plane: Pointer to drm plane
> - * @state: Pointer to the state to be committed
> - * @hw_cmd: rotator command type
> - * return: 0 if success; error code otherwise
> - */
> -static int dpu_plane_rot_submit_command(struct drm_plane *plane,
> - struct drm_plane_state *state, enum dpu_hw_rot_cmd_type hw_cmd)
> -{
> - struct dpu_plane *pdpu = to_dpu_plane(plane);
> - struct dpu_plane_state *pstate = to_dpu_plane_state(state);
> - struct dpu_plane_rot_state *rstate = &pstate->rot;
> - struct dpu_hw_rot_cmd *rot_cmd;
> - struct drm_crtc_state *cstate;
> - struct dpu_crtc_state *dpu_cstate;
> - int ret, i;
> - int fb_mode;
> -
> - if (!plane || !state || !state->fb || !rstate->rot_hw) {
> - DPU_ERROR("invalid parameters\n");
> - return -EINVAL;
> - }
> -
> - cstate = _dpu_plane_get_crtc_state(state);
> - if (IS_ERR_OR_NULL(cstate)) {
> - DPU_ERROR("invalid crtc state %ld\n", PTR_ERR(cstate));
> - return -EINVAL;
> - }
> - dpu_cstate = to_dpu_crtc_state(cstate);
> -
> - rot_cmd = &rstate->rot_cmd;
> -
> - rot_cmd->master = (rstate->out_xpos == 0);
> - rot_cmd->sequence_id = rstate->sequence_id;
> - rot_cmd->fps = pstate->base.crtc && pstate->base.crtc->state ?
> - drm_mode_vrefresh(&pstate->base.crtc->state->adjusted_mode) :
> - DEFAULT_REFRESH_RATE;
> - rot_cmd->rot90 = rstate->rot90;
> - rot_cmd->hflip = rstate->hflip;
> - rot_cmd->vflip = rstate->vflip;
> -
> - rot_cmd->prefill_bw = dpu_crtc_get_property(dpu_cstate,
> - CRTC_PROP_ROT_PREFILL_BW);
> - rot_cmd->clkrate = dpu_crtc_get_property(dpu_cstate,
> - CRTC_PROP_ROT_CLK);
> - rot_cmd->dst_writeback = pdpu->sbuf_writeback;
> -
> - if (dpu_crtc_get_intf_mode(state->crtc) == INTF_MODE_VIDEO)
> - rot_cmd->video_mode = true;
> - else
> - rot_cmd->video_mode = false;
> -
> - rot_cmd->src_pixel_format = state->fb->format->format;
> - rot_cmd->src_modifier = state->fb->modifier;
> - rot_cmd->src_stride = state->fb->pitches[0];
> -
> - rot_cmd->src_format = to_dpu_format(msm_framebuffer_format(state->fb));
> - if (!rot_cmd->src_format) {
> - DPU_ERROR("failed to get src format\n");
> - return -EINVAL;
> - }
> -
> - rot_cmd->src_width = state->fb->width;
> - rot_cmd->src_height = state->fb->height;
> - rot_cmd->src_rect_x = rstate->in_rot_rect.x1 >> 16;
> - rot_cmd->src_rect_y = rstate->in_rot_rect.y1 >> 16;
> - rot_cmd->src_rect_w = drm_rect_width(&rstate->in_rot_rect) >> 16;
> - rot_cmd->src_rect_h = drm_rect_height(&rstate->in_rot_rect) >> 16;
> - rot_cmd->dst_rect_x = 0;
> - rot_cmd->dst_rect_y = 0;
> - rot_cmd->dst_rect_w = drm_rect_width(&rstate->out_rot_rect) >> 16;
> - rot_cmd->dst_rect_h = drm_rect_height(&rstate->out_rot_rect) >> 16;
> -
> - if (hw_cmd == DPU_HW_ROT_CMD_COMMIT) {
> - struct dpu_hw_fmt_layout layout;
> -
> - memset(&layout, 0, sizeof(struct dpu_hw_fmt_layout));
> - dpu_format_populate_layout(pstate->aspace, state->fb,
> - &layout);
> - for (i = 0; i < ARRAY_SIZE(rot_cmd->src_iova); i++) {
> - rot_cmd->src_iova[i] = layout.plane_addr[i];
> - rot_cmd->src_len[i] = layout.plane_size[i];
> - }
> - rot_cmd->src_planes = layout.num_planes;
> -
> - memset(&layout, 0, sizeof(struct dpu_hw_fmt_layout));
> - dpu_format_populate_layout(pstate->aspace, rstate->out_fb,
> - &layout);
> - for (i = 0; i < ARRAY_SIZE(rot_cmd->dst_iova); i++) {
> - rot_cmd->dst_iova[i] = layout.plane_addr[i];
> - rot_cmd->dst_len[i] = layout.plane_size[i];
> - }
> - rot_cmd->dst_planes = layout.num_planes;
> -
> - /* VBIF remapper settings */
> - for (i = 0; i < rstate->rot_hw->caps->xin_count; i++) {
> - const struct dpu_rot_vbif_cfg *cfg =
> - &rstate->rot_hw->caps->vbif_cfg[i];
> -
> - _dpu_plane_inline_rot_set_qos_remap(plane, cfg);
> -
> - if (cfg->is_read) {
> - _dpu_plane_inline_rot_set_ot_limit(plane,
> - state->crtc, cfg, rot_cmd->src_rect_w,
> - rot_cmd->src_rect_h);
> - } else {
> - _dpu_plane_inline_rot_set_ot_limit(plane,
> - state->crtc, cfg, rot_cmd->dst_rect_w,
> - rot_cmd->dst_rect_h);
> - }
> - }
> - }
> -
> - ret = rstate->rot_hw->ops.commit(rstate->rot_hw, rot_cmd, hw_cmd);
> - if (ret)
> - return ret;
> -
> - rstate->out_rotation = rstate->in_rotation;
> - rstate->out_fb_flags = rot_cmd->dst_modifier ?
> - DRM_MODE_FB_MODIFIERS : 0;
> - rstate->out_fb_format = rot_cmd->dst_format;
> - rstate->out_fb_pixel_format = rot_cmd->dst_pixel_format;
> -
> - for (i = 0; i < ARRAY_SIZE(rstate->out_fb_modifier); i++)
> - rstate->out_fb_modifier[i] = rot_cmd->dst_modifier;
> -
> - rstate->out_fb_width = drm_rect_width(&rstate->out_rot_rect) >> 16;
> - rstate->out_fb_height = drm_rect_height(&rstate->out_rot_rect) >> 16;
> - rstate->out_src_x = rstate->out_src_rect.x1 - rstate->out_rot_rect.x1;
> - rstate->out_src_y = rstate->out_src_rect.y1 - rstate->out_rot_rect.y1;
> - rstate->out_src_w = drm_rect_width(&rstate->out_src_rect);
> - rstate->out_src_h = drm_rect_height(&rstate->out_src_rect);
> -
> - if (rot_cmd->rot90)
> - rstate->out_rotation &= ~DRM_MODE_ROTATE_90;
> -
> - if (rot_cmd->hflip)
> - rstate->out_rotation &= ~DRM_MODE_REFLECT_X;
> -
> - if (rot_cmd->vflip)
> - rstate->out_rotation &= ~DRM_MODE_REFLECT_Y;
> -
> - DPU_DEBUG(
> - "plane%d.%d rot:%d/%c%c%c%c/%dx%d/%4.4s/%llx/%dx%d+%d+%d\n",
> - plane->base.id, rstate->sequence_id, hw_cmd,
> - rot_cmd->rot90 ? 'r' : '_',
> - rot_cmd->hflip ? 'h' : '_',
> - rot_cmd->vflip ? 'v' : '_',
> - rot_cmd->video_mode ? 'V' : 'C',
> - state->fb->width, state->fb->height,
> - (char *) &state->fb->format->format,
> - state->fb->modifier,
> - drm_rect_width(&rstate->in_rot_rect) >> 16,
> - drm_rect_height(&rstate->in_rot_rect) >> 16,
> - rstate->in_rot_rect.x1 >> 16,
> - rstate->in_rot_rect.y1 >> 16);
> -
> - DPU_DEBUG("plane%d.%d sspp:%d/%x/%dx%d/%4.4s/%llx/%dx%d+%d+%d\n",
> - plane->base.id, rstate->sequence_id, hw_cmd,
> - rstate->out_rotation,
> - rstate->out_fb_width, rstate->out_fb_height,
> - (char *) &rstate->out_fb_pixel_format,
> - rstate->out_fb_modifier[0],
> - rstate->out_src_w >> 16, rstate->out_src_h >> 16,
> - rstate->out_src_x >> 16, rstate->out_src_y >> 16);
> -
> - return ret;
> -}
> -
> -/**
> - * _dpu_plane_rot_get_fb - attempt to get previously allocated fb/fbo
> - * If an fb/fbo was already created, either from a previous frame or
> - * from another plane in the current commit cycle, attempt to reuse
> - * it for this commit cycle as well.
> - * @plane: Pointer to drm plane
> - * @cstate: Pointer to crtc state
> - * @rstate: Pointer to rotator plane state
> - */
> -static void _dpu_plane_rot_get_fb(struct drm_plane *plane,
> - struct drm_crtc_state *cstate,
> - struct dpu_plane_rot_state *rstate)
> -{
> - struct dpu_kms_fbo *fbo;
> - struct drm_framebuffer *fb;
> -
> - if (!plane || !cstate || !rstate || !rstate->rot_hw)
> - return;
> -
> - fbo = dpu_crtc_res_get(cstate, DPU_CRTC_RES_ROT_OUT_FBO,
> - (u64) &rstate->rot_hw->base);
> - fb = dpu_crtc_res_get(cstate, DPU_CRTC_RES_ROT_OUT_FB,
> - (u64) &rstate->rot_hw->base);
> - if (fb && fbo) {
> - DPU_DEBUG("plane%d.%d get fb/fbo\n", plane->base.id,
> - rstate->sequence_id);
> - } else if (fbo) {
> - dpu_crtc_res_put(cstate, DPU_CRTC_RES_ROT_OUT_FBO,
> - (u64) &rstate->rot_hw->base);
> - fbo = NULL;
> - } else if (fb) {
> - dpu_crtc_res_put(cstate, DPU_CRTC_RES_ROT_OUT_FB,
> - (u64) &rstate->rot_hw->base);
> - fb = NULL;
> - }
> -
> - rstate->out_fbo = fbo;
> - rstate->out_fb = fb;
> -}
> -
> -/**
> - * dpu_plane_rot_prepare_fb - prepare framebuffer of the new state
> - * for rotator (pre-sspp) stage
> - * @plane: Pointer to drm plane
> - * @new_state: Pointer to new drm plane state
> - * return: 0 if success; error code otherwise
> - */
> -static int dpu_plane_rot_prepare_fb(struct drm_plane *plane,
> - struct drm_plane_state *new_state)
> -{
> - struct drm_framebuffer *fb = new_state->fb;
> - struct dpu_plane_state *new_pstate = to_dpu_plane_state(new_state);
> - struct dpu_plane_rot_state *new_rstate = &new_pstate->rot;
> - struct drm_crtc_state *cstate;
> - int ret;
> -
> - DPU_DEBUG("plane%d.%d FB[%u] sbuf:%d rot:%d crtc:%d\n",
> - plane->base.id,
> - new_rstate->sequence_id, fb ? fb->base.id : 0,
> - !!new_rstate->out_sbuf, !!new_rstate->rot_hw,
> - dpu_plane_crtc_enabled(new_state));
> -
> - if (!new_rstate->out_sbuf || !new_rstate->rot_hw)
> - return 0;
> -
> - cstate = _dpu_plane_get_crtc_state(new_state);
> - if (IS_ERR(cstate)) {
> - ret = PTR_ERR(cstate);
> - DPU_ERROR("invalid crtc state %d\n", ret);
> - return ret;
> - }
> -
> - /* need to re-calc based on all newly validated plane states */
> - ret = dpu_plane_rot_calc_cfg(plane, new_state);
> - if (ret)
> - return ret;
> -
> - /* check if stream buffer is already attached to rotator */
> - if (dpu_plane_enabled(new_state) && !new_rstate->out_fb)
> - _dpu_plane_rot_get_fb(plane, cstate, new_rstate);
> -
> - /* create new stream buffer if it is not available */
> - if (dpu_plane_enabled(new_state) && !new_rstate->out_fb) {
> - u32 fb_w = drm_rect_width(&new_rstate->out_rot_rect) >> 16;
> - u32 fb_h = drm_rect_height(&new_rstate->out_rot_rect) >> 16;
> -
> - DPU_DEBUG("plane%d.%d allocate fb/fbo\n", plane->base.id,
> - new_rstate->sequence_id);
> -
> - /* check if out_fb is already attached to rotator */
> - new_rstate->out_fbo = dpu_kms_fbo_alloc(plane->dev, fb_w, fb_h,
> - new_rstate->out_fb_pixel_format,
> - new_rstate->out_fb_modifier,
> - new_rstate->out_fb_flags);
> - if (!new_rstate->out_fbo) {
> - DPU_ERROR("failed to allocate inline buffer object\n");
> - ret = -EINVAL;
> - goto error_create_fbo;
> - }
> -
> - ret = dpu_crtc_res_add(cstate, DPU_CRTC_RES_ROT_OUT_FBO,
> - (u64) &new_rstate->rot_hw->base,
> - new_rstate->out_fbo, &fbo_res_ops);
> - if (ret) {
> - DPU_ERROR("failed to add crtc resource\n");
> - goto error_create_fbo_res;
> - }
> -
> - new_rstate->out_fb = dpu_kms_fbo_create_fb(plane->dev,
> - new_rstate->out_fbo);
> - if (!new_rstate->out_fb) {
> - DPU_ERROR("failed to create inline framebuffer\n");
> - ret = -EINVAL;
> - goto error_create_fb;
> - }
> - DPU_EVT32_VERBOSE(DRMID(plane), new_rstate->sequence_id,
> - new_rstate->out_fb->base.id);
> -
> - ret = dpu_crtc_res_add(cstate, DPU_CRTC_RES_ROT_OUT_FB,
> - (u64) &new_rstate->rot_hw->base,
> - new_rstate->out_fb, &fb_res_ops);
> - if (ret) {
> - DPU_ERROR("failed to add crtc resource %d\n", ret);
> - goto error_create_fb_res;
> - }
> - }
> -
> - /* prepare rotator input buffer */
> - ret = msm_framebuffer_prepare(new_state->fb, new_pstate->aspace);
> - if (ret) {
> - DPU_ERROR("failed to prepare input framebuffer, %d\n", ret);
> - goto error_prepare_input_buffer;
> - }
> -
> - /* prepare rotator output buffer */
> - if (dpu_plane_enabled(new_state) && new_rstate->out_fb) {
> - DPU_DEBUG("plane%d.%d prepare fb/fbo\n", plane->base.id,
> - new_rstate->sequence_id);
> -
> - ret = msm_framebuffer_prepare(new_rstate->out_fb,
> - new_pstate->aspace);
> - if (ret) {
> - DPU_ERROR("failed to prepare inline framebuffer, %d\n",
> - ret);
> - goto error_prepare_output_buffer;
> - }
> - }
> -
> - return 0;
> -
> -error_prepare_output_buffer:
> - msm_framebuffer_cleanup(new_state->fb, new_pstate->aspace);
> -error_prepare_input_buffer:
> - dpu_crtc_res_put(cstate, DPU_CRTC_RES_ROT_OUT_FB,
> - (u64) &new_rstate->rot_hw->base);
> -error_create_fb_res:
> - new_rstate->out_fb = NULL;
> -error_create_fb:
> - dpu_crtc_res_put(cstate, DPU_CRTC_RES_ROT_OUT_FBO,
> - (u64) &new_rstate->rot_hw->base);
> -error_create_fbo_res:
> - new_rstate->out_fbo = NULL;
> -error_create_fbo:
> - return ret;
> -}
> -
> -/**
> - * dpu_plane_rot_cleanup_fb - cleanup framebuffer of previous state for the
> - * rotator (pre-sspp) stage
> - * @plane: Pointer to drm plane
> - * @old_state: Pointer to previous drm plane state
> - * return: none
> - */
> -static void dpu_plane_rot_cleanup_fb(struct drm_plane *plane,
> - struct drm_plane_state *old_state)
> -{
> - struct dpu_plane_state *old_pstate = to_dpu_plane_state(old_state);
> - struct dpu_plane_rot_state *old_rstate = &old_pstate->rot;
> - struct dpu_hw_rot_cmd *cmd = &old_rstate->rot_cmd;
> - struct drm_crtc_state *cstate;
> - int ret;
> -
> - DPU_DEBUG("plane%d.%d FB[%u] sbuf:%d rot:%d crtc:%d\n", plane->base.id,
> - old_rstate->sequence_id, old_state->fb->base.id,
> - !!old_rstate->out_sbuf, !!old_rstate->rot_hw,
> - dpu_plane_crtc_enabled(old_state));
> -
> - if (!old_rstate->out_sbuf || !old_rstate->rot_hw)
> - return;
> -
> - cstate = _dpu_plane_get_crtc_state(old_state);
> - if (IS_ERR(cstate)) {
> - ret = PTR_ERR(cstate);
> - DPU_ERROR("invalid crtc state %d\n", ret);
> - return;
> - }
> -
> - if (dpu_plane_crtc_enabled(old_state)) {
> - ret = old_rstate->rot_hw->ops.commit(old_rstate->rot_hw, cmd,
> - DPU_HW_ROT_CMD_CLEANUP);
> - if (ret)
> - DPU_ERROR("failed to cleanup rotator buffers\n");
> - }
> -
> - if (dpu_plane_enabled(old_state)) {
> - if (old_rstate->out_fb) {
> - msm_framebuffer_cleanup(old_rstate->out_fb,
> - old_pstate->aspace);
> - dpu_crtc_res_put(cstate, DPU_CRTC_RES_ROT_OUT_FB,
> - (u64) &old_rstate->rot_hw->base);
> - old_rstate->out_fb = NULL;
> - dpu_crtc_res_put(cstate, DPU_CRTC_RES_ROT_OUT_FBO,
> - (u64) &old_rstate->rot_hw->base);
> - old_rstate->out_fbo = NULL;
> - }
> -
> - msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
> - }
> -}
> -
> -/**
> - * dpu_plane_rot_atomic_check - verify rotator update of the given state
> - * @plane: Pointer to drm plane
> - * @state: Pointer to drm plane state to be validated
> - * return: 0 if success; error code otherwise
> - */
> -static int dpu_plane_rot_atomic_check(struct drm_plane *plane,
> - struct drm_plane_state *state)
> -{
> - struct dpu_plane *pdpu;
> - struct dpu_plane_state *pstate, *old_pstate;
> - struct dpu_plane_rot_state *rstate, *old_rstate;
> - struct drm_crtc_state *cstate;
> - struct dpu_hw_blk *hw_blk;
> - int i, ret = 0;
> -
> - if (!plane || !state) {
> - DPU_ERROR("invalid plane/state\n");
> - return -EINVAL;
> - }
> -
> - pdpu = to_dpu_plane(plane);
> - pstate = to_dpu_plane_state(state);
> - old_pstate = to_dpu_plane_state(plane->state);
> - rstate = &pstate->rot;
> - old_rstate = &old_pstate->rot;
> -
> - /* cstate will be null if crtc is disconnected from plane */
> - cstate = _dpu_plane_get_crtc_state(state);
> - if (IS_ERR(cstate)) {
> - ret = PTR_ERR(cstate);
> - DPU_ERROR("invalid crtc state %d\n", ret);
> - return ret;
> - }
> -
> - DPU_DEBUG("plane%d.%d FB[%u] sbuf:%d rot:%d crtc:%d\n", plane->base.id,
> - rstate->sequence_id, state->fb ? state->fb->base.id : 0,
> - !!rstate->out_sbuf, !!rstate->rot_hw,
> - dpu_plane_crtc_enabled(state));
> -
> - rstate->in_rotation = drm_rotation_simplify(
> - dpu_plane_get_property(pstate, PLANE_PROP_ROTATION),
> - DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
> - DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
> - rstate->rot90 = rstate->in_rotation & DRM_MODE_ROTATE_90 ? true : false;
> - rstate->hflip = rstate->in_rotation & DRM_MODE_REFLECT_X ? true : false;
> - rstate->vflip = rstate->in_rotation & DRM_MODE_REFLECT_Y ? true : false;
> - rstate->out_sbuf = pdpu->sbuf_mode || rstate->rot90;
> -
> - if (dpu_plane_enabled(state) && rstate->out_sbuf) {
> - DPU_DEBUG("plane%d.%d acquire rotator, fb %d\n",
> - plane->base.id, rstate->sequence_id,
> - state->fb ? state->fb->base.id : -1);
> -
> - hw_blk = dpu_crtc_res_get(cstate, DPU_HW_BLK_ROT,
> - (u64) state->fb);
> - if (!hw_blk) {
> - DPU_ERROR("plane%d.%d no available rotator, fb %d\n",
> - plane->base.id, rstate->sequence_id,
> - state->fb ? state->fb->base.id : -1);
> - DPU_EVT32(DRMID(plane), rstate->sequence_id,
> - DPU_EVTLOG_ERROR);
> - return -EINVAL;
> - }
> -
> - rstate->rot_hw = to_dpu_hw_rot(hw_blk);
> -
> - if (!rstate->rot_hw->ops.commit) {
> - DPU_ERROR("plane%d.%d invalid rotator ops\n",
> - plane->base.id, rstate->sequence_id);
> - dpu_crtc_res_put(cstate,
> - DPU_HW_BLK_ROT, (u64) state->fb);
> - rstate->rot_hw = NULL;
> - return -EINVAL;
> - }
> -
> - rstate->in_fb = state->fb;
> - } else {
> - rstate->in_fb = NULL;
> - rstate->rot_hw = NULL;
> - }
> -
> - if (dpu_plane_enabled(state) && rstate->out_sbuf && rstate->rot_hw) {
> - uint32_t fb_id;
> -
> - fb_id = state->fb ? state->fb->base.id : -1;
> - DPU_DEBUG("plane%d.%d use rotator, fb %d\n",
> - plane->base.id, rstate->sequence_id, fb_id);
> -
> - ret = dpu_plane_rot_calc_cfg(plane, state);
> - if (ret)
> - return ret;
> -
> - ret = dpu_plane_rot_submit_command(plane, state,
> - DPU_HW_ROT_CMD_VALIDATE);
> - if (ret)
> - return ret;
> -
> - if (rstate->nplane != old_rstate->nplane ||
> - rstate->out_xpos != old_rstate->out_xpos)
> - pstate->dirty |= DPU_PLANE_DIRTY_FORMAT |
> - DPU_PLANE_DIRTY_RECTS;
> -
> - /* check if stream buffer is already attached to rotator */
> - _dpu_plane_rot_get_fb(plane, cstate, rstate);
> -
> - /* release buffer if output format configuration changes */
> - if (rstate->out_fb &&
> - ((rstate->out_fb_height != rstate->out_fb->height) ||
> - (rstate->out_fb_width != rstate->out_fb->width) ||
> - (rstate->out_fb_pixel_format !=
> - rstate->out_fb->format->format) ||
> - (rstate->out_fb_modifier[0] !=
> - rstate->out_fb->modifier) ||
> - (rstate->out_fb_flags != rstate->out_fb->flags))) {
> -
> - DPU_DEBUG("plane%d.%d release fb/fbo\n", plane->base.id,
> - rstate->sequence_id);
> - DPU_EVT32_VERBOSE(DRMID(plane),
> - rstate->sequence_id, fb_id);
> -
> - dpu_crtc_res_put(cstate, DPU_CRTC_RES_ROT_OUT_FB,
> - (u64) &rstate->rot_hw->base);
> - rstate->out_fb = NULL;
> - dpu_crtc_res_put(cstate, DPU_CRTC_RES_ROT_OUT_FBO,
> - (u64) &rstate->rot_hw->base);
> - rstate->out_fbo = NULL;
> - }
> - } else {
> -
> - DPU_DEBUG("plane%d.%d bypass rotator\n", plane->base.id,
> - rstate->sequence_id);
> -
> - /* bypass rotator - initialize output setting as input */
> - for (i = 0; i < ARRAY_SIZE(rstate->out_fb_modifier); i++)
> - rstate->out_fb_modifier[i] = state->fb ?
> - state->fb->modifier : 0x0;
> -
> - if (state->fb) {
> - rstate->out_fb_pixel_format = state->fb->format->format;
> - rstate->out_fb_flags = state->fb->flags;
> - rstate->out_fb_width = state->fb->width;
> - rstate->out_fb_height = state->fb->height;
> - } else {
> - rstate->out_fb_pixel_format = 0x0;
> - rstate->out_fb_flags = 0x0;
> - rstate->out_fb_width = 0;
> - rstate->out_fb_height = 0;
> - }
> -
> - rstate->out_rotation = rstate->in_rotation;
> - rstate->out_src_x = state->src_x;
> - rstate->out_src_y = state->src_y;
> - rstate->out_src_w = state->src_w;
> - rstate->out_src_h = state->src_h;
> -
> - rstate->out_fb_format = NULL;
> - rstate->out_sbuf = false;
> - rstate->out_fb = state->fb;
> - }
> -
> - return ret;
> -}
> -
> -/**
> - * dpu_plane_rot_atomic_update - perform atomic update for rotator stage
> - * @plane: Pointer to drm plane
> - * @old_state: Pointer to previous state
> - * return: none
> - */
> -static void dpu_plane_rot_atomic_update(struct drm_plane *plane,
> - struct drm_plane_state *old_state)
> -{
> - struct drm_plane_state *state;
> - struct dpu_plane_state *pstate;
> - struct dpu_plane_rot_state *rstate;
> - int ret = 0;
> -
> - if (!plane || !plane->state) {
> - DPU_ERROR("invalid plane/state\n");
> - return;
> - }
> -
> - state = plane->state;
> - pstate = to_dpu_plane_state(state);
> - rstate = &pstate->rot;
> -
> - DPU_DEBUG("plane%d.%d sbuf:%d rot:%d crtc:%d\n", plane->base.id,
> - rstate->sequence_id,
> - !!rstate->out_sbuf, !!rstate->rot_hw,
> - dpu_plane_crtc_enabled(plane->state));
> -
> - if (!dpu_plane_crtc_enabled(state))
> - return;
> -
> - if (!rstate->out_sbuf || !rstate->rot_hw)
> - return;
> -
> - dpu_plane_rot_submit_command(plane, state, DPU_HW_ROT_CMD_COMMIT);
> -
> - return;
> -
> -error_prepare_output_buffer:
> - msm_framebuffer_cleanup(state->fb, pstate->aspace);
> -}
> -
> -void dpu_plane_kickoff(struct drm_plane *plane)
> -{
> - struct dpu_plane_state *pstate;
> -
> - if (!plane || !plane->state) {
> - DPU_ERROR("invalid plane\n");
> - return;
> - }
> -
> - pstate = to_dpu_plane_state(plane->state);
> -
> - if (!pstate->rot.rot_hw || !pstate->rot.rot_hw->ops.commit)
> - return;
> -
> - pstate->rot.rot_hw->ops.commit(pstate->rot.rot_hw,
> - &pstate->rot.rot_cmd,
> - DPU_HW_ROT_CMD_START);
> -}
> -
> -/**
> - * dpu_plane_rot_destroy_state - destroy state for rotator stage
> - * @plane: Pointer to drm plane
> - * @state: Pointer to state to be destroyed
> - * return: none
> - */
> -static void dpu_plane_rot_destroy_state(struct drm_plane *plane,
> - struct drm_plane_state *state)
> -{
> - struct dpu_plane_state *pstate = to_dpu_plane_state(state);
> - struct dpu_plane_rot_state *rstate = &pstate->rot;
> -
> - DPU_DEBUG("plane%d.%d sbuf:%d rot:%d crtc:%d\n", plane->base.id,
> - rstate->sequence_id,
> - !!rstate->out_sbuf, !!rstate->rot_hw,
> - dpu_plane_crtc_enabled(state));
> -}
> -
> -/**
> - * dpu_plane_rot_duplicate_state - duplicate state for rotator stage
> - * @plane: Pointer to drm plane
> - * @new_state: Pointer to duplicated state
> - * return: 0 if success; error code otherwise
> - */
> -static int dpu_plane_rot_duplicate_state(struct drm_plane *plane,
> - struct drm_plane_state *new_state)
> -{
> - struct dpu_plane_state *pstate = to_dpu_plane_state(new_state);
> - struct dpu_plane_rot_state *rstate = &pstate->rot;
> -
> - rstate->sequence_id++;
> -
> - DPU_DEBUG("plane%d.%d sbuf:%d rot:%d\n", plane->base.id,
> - rstate->sequence_id,
> - !!rstate->out_sbuf, !!rstate->rot_hw);
> -
> - rstate->rot_hw = NULL;
> - rstate->out_fb = NULL;
> - rstate->out_fbo = NULL;
> -
> - return 0;
> -}
> -
> -/**
> - * dpu_plane_rot_install_caps - install plane rotator capabilities
> - * @plane: Pointer to drm plane
> - * return: none
> - */
> -static void dpu_plane_rot_install_caps(struct drm_plane *plane)
> -{
> - struct dpu_plane *pdpu = to_dpu_plane(plane);
> - const struct dpu_format_extended *format_list;
> - struct dpu_kms_info *info;
> - struct dpu_hw_rot *rot_hw;
> - const char *downscale_caps;
> -
> - if (!pdpu->catalog || !(pdpu->features & BIT(DPU_SSPP_SBUF)) ||
> - !pdpu->catalog->rot_count)
> - return;
> -
> - if (pdpu->blob_rot_caps)
> - return;
> -
> - info = kzalloc(sizeof(struct dpu_kms_info), GFP_KERNEL);
> - if (!info)
> - return;
> -
> - rot_hw = dpu_hw_rot_get(NULL);
> - if (!rot_hw || !rot_hw->ops.get_format_caps ||
> - !rot_hw->ops.get_downscale_caps) {
> - DPU_ERROR("invalid rotator hw\n");
> - goto error_rot;
> - }
> -
> - dpu_kms_info_reset(info);
> -
> - format_list = rot_hw->ops.get_format_caps(rot_hw);
> - if (format_list) {
> - dpu_kms_info_start(info, "pixel_formats");
> - while (format_list->fourcc_format) {
> - dpu_kms_info_append_format(info,
> - format_list->fourcc_format,
> - format_list->modifier);
> - ++format_list;
> - }
> - dpu_kms_info_stop(info);
> - }
> -
> - downscale_caps = rot_hw->ops.get_downscale_caps(rot_hw);
> - if (downscale_caps) {
> - dpu_kms_info_start(info, "downscale_ratios");
> - dpu_kms_info_append(info, downscale_caps);
> - dpu_kms_info_stop(info);
> - }
> -
> - if (rot_hw->ops.get_cache_size)
> - dpu_kms_info_add_keyint(info, "cache_size",
> - rot_hw->ops.get_cache_size(rot_hw));
> -
> - if (rot_hw->ops.get_maxlinewidth)
> - dpu_kms_info_add_keyint(info, "max_linewidth",
> - rot_hw->ops.get_maxlinewidth(rot_hw));
> -
> - msm_property_set_blob(&pdpu->property_info, &pdpu->blob_rot_caps,
> - info->data, DPU_KMS_INFO_DATALEN(info),
> - PLANE_PROP_ROT_CAPS_V1);
> -
> - dpu_hw_rot_put(rot_hw);
> -error_rot:
> - kfree(info);
> -}
> -
> -/**
> - * dpu_plane_rot_install_properties - install plane rotator properties
> - * @plane: Pointer to drm plane
> - * @catalog: Pointer to mdss configuration
> - * return: none
> - */
> -static void dpu_plane_rot_install_properties(struct drm_plane *plane,
> - struct dpu_mdss_cfg *catalog)
> -{
> - struct dpu_plane *pdpu = to_dpu_plane(plane);
> - unsigned long supported_rotations = DRM_MODE_ROTATE_0 |
> - DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
> -
> - if (!plane || !pdpu) {
> - DPU_ERROR("invalid plane\n");
> - return;
> - } else if (!catalog) {
> - DPU_ERROR("invalid catalog\n");
> - return;
> - }
> -
> - if ((pdpu->features & BIT(DPU_SSPP_SBUF)) && catalog->rot_count)
> - supported_rotations |= DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
> - DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
> -
> - msm_property_install_rotation(&pdpu->property_info, plane,
> - DRM_MODE_ROTATE_0, supported_rotations,
> - PLANE_PROP_ROTATION);
> -
> - if (!(pdpu->features & BIT(DPU_SSPP_SBUF)) || !catalog->rot_count)
> - return;
> -
> - msm_property_install_range(&pdpu->property_info, "rot_dst_x",
> - 0, 0, U64_MAX, 0, PLANE_PROP_ROT_DST_X);
> - msm_property_install_range(&pdpu->property_info, "rot_dst_y",
> - 0, 0, U64_MAX, 0, PLANE_PROP_ROT_DST_Y);
> - msm_property_install_range(&pdpu->property_info, "rot_dst_w",
> - 0, 0, U64_MAX, 0, PLANE_PROP_ROT_DST_W);
> - msm_property_install_range(&pdpu->property_info, "rot_dst_h",
> - 0, 0, U64_MAX, 0, PLANE_PROP_ROT_DST_H);
> - msm_property_install_blob(&pdpu->property_info, "rot_caps_v1",
> - DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_ROT_CAPS_V1);
> -}
> -
> void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state)
> {
> struct dpu_plane_state *pstate;
> @@ -2684,13 +1454,11 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
> * @plane: Pointer to drm plane structure
> * @ctl: Pointer to hardware control driver
> * @flush_sspp: Pointer to sspp flush control word
> - * @flush_rot: Pointer to rotator flush control word
> */
> void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
> - u32 *flush_sspp, u32 *flush_rot)
> + u32 *flush_sspp)
> {
> struct dpu_plane_state *pstate;
> - struct dpu_plane_rot_state *rstate;
>
> if (!plane || !flush_sspp) {
> DPU_ERROR("invalid parameters\n");
> @@ -2698,17 +1466,8 @@ void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
> }
>
> pstate = to_dpu_plane_state(plane->state);
> - rstate = &pstate->rot;
>
> *flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane));
> -
> - if (!flush_rot)
> - return;
> -
> - *flush_rot = 0x0;
> - if (rstate && rstate->out_sbuf && rstate->rot_hw &&
> - ctl->ops.get_bitmask_rot)
> - ctl->ops.get_bitmask_rot(ctl, flush_rot, rstate->rot_hw->idx);
> }
>
> static int dpu_plane_prepare_fb(struct drm_plane *plane,
> @@ -2717,7 +1476,6 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane,
> struct drm_framebuffer *fb = new_state->fb;
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> struct dpu_plane_state *pstate = to_dpu_plane_state(new_state);
> - struct dpu_plane_rot_state *new_rstate;
> struct dpu_hw_fmt_layout layout;
> struct msm_gem_address_space *aspace;
> int ret;
> @@ -2736,16 +1494,8 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane,
> /* cache aspace */
> pstate->aspace = aspace;
>
> - ret = dpu_plane_rot_prepare_fb(plane, new_state);
> - if (ret) {
> - DPU_ERROR("failed to prepare rot framebuffer\n");
> - return ret;
> - }
> -
> - new_rstate = &to_dpu_plane_state(new_state)->rot;
> -
> if (pstate->aspace) {
> - ret = msm_framebuffer_prepare(new_rstate->out_fb,
> + ret = msm_framebuffer_prepare(new_state->fb,
> pstate->aspace);
> if (ret) {
> DPU_ERROR("failed to prepare framebuffer\n");
> @@ -2755,7 +1505,7 @@ static int dpu_plane_prepare_fb(struct drm_plane *plane,
>
> /* validate framebuffer layout before commit */
> ret = dpu_format_populate_layout(pstate->aspace,
> - new_rstate->out_fb, &layout);
> + new_state->fb, &layout);
> if (ret) {
> DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret);
> return ret;
> @@ -2769,7 +1519,6 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane,
> {
> struct dpu_plane *pdpu = to_dpu_plane(plane);
> struct dpu_plane_state *old_pstate;
> - struct dpu_plane_rot_state *old_rstate;
>
> if (!old_state || !old_state->fb)
> return;
> @@ -2778,11 +1527,7 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane,
>
> DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id);
>
> - old_rstate = &old_pstate->rot;
> -
> - msm_framebuffer_cleanup(old_rstate->out_fb, old_pstate->aspace);
> -
> - dpu_plane_rot_cleanup_fb(plane, old_state);
> + msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
> }
>
> static void _dpu_plane_sspp_atomic_check_mode_changed(struct dpu_plane *pdpu,
> @@ -2791,8 +1536,6 @@ static void _dpu_plane_sspp_atomic_check_mode_changed(struct dpu_plane *pdpu,
> {
> struct dpu_plane_state *pstate = to_dpu_plane_state(state);
> struct dpu_plane_state *old_pstate = to_dpu_plane_state(old_state);
> - struct dpu_plane_rot_state *rstate = &pstate->rot;
> - struct dpu_plane_rot_state *old_rstate = &old_pstate->rot;
> struct drm_framebuffer *fb, *old_fb;
>
> /* no need to check it again */
> @@ -2811,12 +1554,6 @@ static void _dpu_plane_sspp_atomic_check_mode_changed(struct dpu_plane *pdpu,
> pstate->multirect_mode != old_pstate->multirect_mode) {
> DPU_DEBUG_PLANE(pdpu, "multirect config updated\n");
> pstate->dirty |= DPU_PLANE_DIRTY_ALL;
> - } else if (rstate->out_src_w != old_rstate->out_src_w ||
> - rstate->out_src_h != old_rstate->out_src_h ||
> - rstate->out_src_x != old_rstate->out_src_x ||
> - rstate->out_src_y != old_rstate->out_src_y) {
> - DPU_DEBUG_PLANE(pdpu, "src rect updated\n");
> - pstate->dirty |= DPU_PLANE_DIRTY_RECTS;
> } else if (state->crtc_w != old_state->crtc_w ||
> state->crtc_h != old_state->crtc_h ||
> state->crtc_x != old_state->crtc_x ||
> @@ -2831,8 +1568,8 @@ static void _dpu_plane_sspp_atomic_check_mode_changed(struct dpu_plane *pdpu,
> pstate->dirty |= DPU_PLANE_DIRTY_RECTS;
> }
>
> - fb = rstate->out_fb;
> - old_fb = old_rstate->out_fb;
> + fb = state->fb;
> + old_fb = old_state->fb;
>
> if (!fb || !old_fb) {
> DPU_DEBUG_PLANE(pdpu, "can't compare fb handles\n");
> @@ -2982,7 +1719,6 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
> int ret = 0;
> struct dpu_plane *pdpu;
> struct dpu_plane_state *pstate;
> - struct dpu_plane_rot_state *rstate;
> const struct dpu_format *fmt;
> struct dpu_rect src, dst;
> uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
> @@ -2998,7 +1734,6 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
>
> pdpu = to_dpu_plane(plane);
> pstate = to_dpu_plane_state(state);
> - rstate = &pstate->rot;
>
> if (!pdpu->pipe_sblk) {
> DPU_ERROR_PLANE(pdpu, "invalid catalog\n");
> @@ -3010,8 +1745,8 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
> deci_h = dpu_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
>
> /* src values are in Q16 fixed point, convert to integer */
> - POPULATE_RECT(&src, rstate->out_src_x, rstate->out_src_y,
> - rstate->out_src_w, rstate->out_src_h, q16_data);
> + POPULATE_RECT(&src, state->src_x, state->src_y, state->src_w,
> + state->src_h, q16_data);
> POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
> state->crtc_h, !q16_data);
>
> @@ -3028,18 +1763,6 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
> if (!dpu_plane_enabled(state))
> goto modeset_update;
>
> - DPU_DEBUG(
> - "plane%d.%u sspp:%x/%dx%d/%4.4s/%llx/%dx%d+%d+%d crtc:%dx%d+%d+%d\n",
> - plane->base.id, rstate->sequence_id,
> - rstate->out_rotation,
> - rstate->out_fb_width, rstate->out_fb_height,
> - (char *) &rstate->out_fb_pixel_format,
> - rstate->out_fb_modifier[0],
> - rstate->out_src_w >> 16, rstate->out_src_h >> 16,
> - rstate->out_src_x >> 16, rstate->out_src_y >> 16,
> - state->crtc_w, state->crtc_h,
> - state->crtc_x, state->crtc_y);
> -
> fmt = to_dpu_format(msm_framebuffer_format(state->fb));
>
> min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
> @@ -3053,11 +1776,11 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
> ret = -EINVAL;
>
> /* check src bounds */
> - } else if (rstate->out_fb_width > MAX_IMG_WIDTH ||
> - rstate->out_fb_height > MAX_IMG_HEIGHT ||
> + } else if (state->fb->width > MAX_IMG_WIDTH ||
> + state->fb->height > MAX_IMG_HEIGHT ||
> src.w < min_src_size || src.h < min_src_size ||
> - CHECK_LAYER_BOUNDS(src.x, src.w, rstate->out_fb_width) ||
> - CHECK_LAYER_BOUNDS(src.y, src.h, rstate->out_fb_height)) {
> + CHECK_LAYER_BOUNDS(src.x, src.w, state->fb->width) ||
> + CHECK_LAYER_BOUNDS(src.y, src.h, state->fb->height)) {
> DPU_ERROR_PLANE(pdpu, "invalid source %u, %u, %ux%u\n",
> src.x, src.y, src.w, src.h);
> ret = -E2BIG;
> @@ -3112,8 +1835,8 @@ static int dpu_plane_sspp_atomic_check(struct drm_plane *plane,
> src_deci_w, src_deci_h, dst.w, dst.h);
> ret = -E2BIG;
> } else if (_dpu_plane_validate_scaler_v2(pdpu, pstate, fmt,
> - rstate->out_fb_width,
> - rstate->out_fb_height,
> + state->fb->width,
> + state->fb->height,
> src.w, src.h, deci_w, deci_h)) {
> ret = -EINVAL;
> }
> @@ -3170,10 +1893,6 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
>
> DPU_DEBUG_PLANE(pdpu, "\n");
>
> - ret = dpu_plane_rot_atomic_check(plane, state);
> - if (ret)
> - goto exit;
> -
> ret = dpu_plane_sspp_atomic_check(plane, state);
>
> exit:
> @@ -3238,7 +1957,6 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
> struct drm_plane_state *state;
> struct dpu_plane_state *pstate;
> struct dpu_plane_state *old_pstate;
> - struct dpu_plane_rot_state *rstate;
> const struct dpu_format *fmt;
> struct drm_crtc *crtc;
> struct drm_framebuffer *fb;
> @@ -3261,12 +1979,11 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
> state = plane->state;
>
> pstate = to_dpu_plane_state(state);
> - rstate = &pstate->rot;
>
> old_pstate = to_dpu_plane_state(old_state);
>
> crtc = state->crtc;
> - fb = rstate->out_fb;
> + fb = state->fb;
> if (!crtc || !fb) {
> DPU_ERROR_PLANE(pdpu, "invalid crtc %d or fb %d\n",
> crtc != 0, fb != 0);
> @@ -3275,18 +1992,6 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
> fmt = to_dpu_format(msm_framebuffer_format(fb));
> nplanes = fmt->num_planes;
>
> - DPU_DEBUG(
> - "plane%d.%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
> - plane->base.id, rstate->sequence_id,
> - rstate->out_fb_width, rstate->out_fb_height,
> - (char *) &rstate->out_fb_pixel_format,
> - rstate->out_fb_modifier[0],
> - rstate->out_src_w >> 16, rstate->out_src_h >> 16,
> - rstate->out_src_x >> 16, rstate->out_src_y >> 16,
> - rstate->out_rotation,
> - state->crtc_w, state->crtc_h,
> - state->crtc_x, state->crtc_y);
> -
> /* force reprogramming of all the parameters, if the flag is set */
> if (pdpu->revalidate) {
> DPU_DEBUG("plane:%d - reconfigure all the parameters\n",
> @@ -3318,9 +2023,6 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
> /* potentially need to refresh everything */
> pstate->dirty = DPU_PLANE_DIRTY_ALL;
> break;
> - case PLANE_PROP_ROTATION:
> - pstate->dirty |= DPU_PLANE_DIRTY_FORMAT;
> - break;
> case PLANE_PROP_INFO:
> case PLANE_PROP_ALPHA:
> case PLANE_PROP_INPUT_FENCE:
> @@ -3331,12 +2033,6 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
> case PLANE_PROP_PREFILL_TIME:
> pstate->dirty |= DPU_PLANE_DIRTY_PERF;
> break;
> - case PLANE_PROP_ROT_DST_X:
> - case PLANE_PROP_ROT_DST_Y:
> - case PLANE_PROP_ROT_DST_W:
> - case PLANE_PROP_ROT_DST_H:
> - /* handled by rotator atomic update */
> - break;
> default:
> /* unknown property, refresh everything */
> pstate->dirty |= DPU_PLANE_DIRTY_ALL;
> @@ -3371,8 +2067,8 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
>
> /* update roi config */
> if (pstate->dirty & DPU_PLANE_DIRTY_RECTS) {
> - POPULATE_RECT(&src, rstate->out_src_x, rstate->out_src_y,
> - rstate->out_src_w, rstate->out_src_h, q16_data);
> + POPULATE_RECT(&src, state->src_x, state->src_y,
> + state->src_w, state->src_h, q16_data);
> POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
> state->crtc_w, state->crtc_h, !q16_data);
>
> @@ -3442,11 +2138,6 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
> if ((pstate->dirty & DPU_PLANE_DIRTY_FORMAT) &&
> pdpu->pipe_hw->ops.setup_format) {
> src_flags = 0x0;
> - DPU_DEBUG_PLANE(pdpu, "rotation 0x%X\n", rstate->out_rotation);
> - if (rstate->out_rotation & DRM_MODE_REFLECT_X)
> - src_flags |= DPU_SSPP_FLIP_LR;
> - if (rstate->out_rotation & DRM_MODE_REFLECT_Y)
> - src_flags |= DPU_SSPP_FLIP_UD;
>
> /* update format */
> pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags,
> @@ -3469,38 +2160,6 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane,
> pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg);
> }
>
> - if (pdpu->pipe_hw->ops.setup_sys_cache) {
> - if (rstate->out_sbuf && rstate->rot_hw) {
> - if (rstate->nplane < 2)
> - pstate->sc_cfg.op_mode =
> - DPU_PIPE_SC_OP_MODE_INLINE_SINGLE;
> - else if (rstate->out_xpos == 0)
> - pstate->sc_cfg.op_mode =
> - DPU_PIPE_SC_OP_MODE_INLINE_LEFT;
> - else
> - pstate->sc_cfg.op_mode =
> - DPU_PIPE_SC_OP_MODE_INLINE_RIGHT;
> -
> - pstate->sc_cfg.rd_en = true;
> - pstate->sc_cfg.rd_scid =
> - rstate->rot_hw->caps->scid;
> - pstate->sc_cfg.rd_noallocate = true;
> - pstate->sc_cfg.rd_op_type =
> - DPU_PIPE_SC_RD_OP_TYPE_CACHEABLE;
> - } else {
> - pstate->sc_cfg.op_mode =
> - DPU_PIPE_SC_OP_MODE_OFFLINE;
> - pstate->sc_cfg.rd_en = false;
> - pstate->sc_cfg.rd_scid = 0;
> - pstate->sc_cfg.rd_noallocate = true;
> - pstate->sc_cfg.rd_op_type =
> - DPU_PIPE_SC_RD_OP_TYPE_CACHEABLE;
> - }
> -
> - pdpu->pipe_hw->ops.setup_sys_cache(
> - pdpu->pipe_hw, &pstate->sc_cfg);
> - }
> -
> /* update csc */
> if (DPU_FORMAT_IS_YUV(fmt))
> _dpu_plane_setup_csc(pdpu);
> @@ -3593,8 +2252,6 @@ static void dpu_plane_atomic_update(struct drm_plane *plane,
>
> DPU_DEBUG_PLANE(pdpu, "\n");
>
> - dpu_plane_rot_atomic_update(plane, old_state);
> -
> if (!dpu_plane_sspp_enabled(state)) {
> _dpu_plane_atomic_disable(plane, old_state);
> } else {
> @@ -3757,8 +2414,6 @@ static void _dpu_plane_install_properties(struct drm_plane *plane,
> msm_property_install_volatile_range(&pdpu->property_info,
> "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
>
> - dpu_plane_rot_install_properties(plane, catalog);
> -
> msm_property_install_enum(&pdpu->property_info, "blend_op", 0x0, 0,
> e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP);
>
> @@ -4086,15 +2741,6 @@ static int dpu_plane_atomic_set_property(struct drm_plane *plane,
> return ret;
> }
>
> -static int dpu_plane_set_property(struct drm_plane *plane,
> - struct drm_property *property, uint64_t val)
> -{
> - DPU_DEBUG("\n");
> -
> - return dpu_plane_atomic_set_property(plane,
> - plane->state, property, val);
> -}
> -
> static int dpu_plane_atomic_get_property(struct drm_plane *plane,
> const struct drm_plane_state *state,
> struct drm_property *property, uint64_t *val)
> @@ -4110,9 +2756,6 @@ static int dpu_plane_atomic_get_property(struct drm_plane *plane,
> } else {
> DPU_DEBUG_PLANE(pdpu, "\n");
> pstate = to_dpu_plane_state(state);
> -#ifdef CONFIG_QCOM_DPU_ROT
> - dpu_plane_rot_install_caps(plane);
> -#endif
> ret = msm_property_atomic_get(&pdpu->property_info,
> &pstate->property_state, property, val);
> }
> @@ -4163,8 +2806,6 @@ static void dpu_plane_destroy_state(struct drm_plane *plane,
>
> DPU_DEBUG_PLANE(pdpu, "\n");
>
> - dpu_plane_rot_destroy_state(plane, &pstate->base);
> -
> /* remove ref count for frame buffers */
> if (state->fb)
> drm_framebuffer_put(state->fb);
> @@ -4226,8 +2867,6 @@ static void dpu_plane_destroy_state(struct drm_plane *plane,
>
> __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
>
> - dpu_plane_rot_duplicate_state(plane, &pstate->base);
> -
> return &pstate->base;
> }
>
> @@ -4455,13 +3094,6 @@ static int _dpu_plane_init_debugfs(struct drm_plane *plane)
> 0600,
> pdpu->debugfs_root,
> kms, &dpu_plane_danger_enable);
> - debugfs_create_u32("sbuf_mode",
> - 0600,
> - pdpu->debugfs_root, &pdpu->sbuf_mode);
> - debugfs_create_u32("sbuf_writeback",
> - 0600,
> - pdpu->debugfs_root,
> - &pdpu->sbuf_writeback);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> index ad9d5cf..25b6b15 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> @@ -24,71 +24,8 @@
> #include "msm_prop.h"
> #include "dpu_kms.h"
> #include "dpu_hw_mdss.h"
> -#include "dpu_hw_rot.h"
> #include "dpu_hw_sspp.h"
>
> -/**
> - * struct dpu_plane_rot_state - state of pre-sspp rotator stage
> - * @sequence_id: sequence identifier, incremented per state duplication
> - * @rot_hw: Pointer to rotator hardware driver
> - * @rot90: true if rotation of 90 degree is required
> - * @hflip: true if horizontal flip is required
> - * @vflip: true if vertical flip is required
> - * @rot_cmd: rotator configuration command
> - * @nplane: total number of drm plane attached to rotator
> - * @in_fb: input fb attached to rotator
> - * @in_rotation: input rotation property of rotator stage
> - * @in_rot_rect: input rectangle of the rotator in plane fb coordinate
> - * @out_rotation: output rotation property of rotator stage
> - * @out_rot_rect: output rectangle of the rotator in plane fb coordinate
> - * @out_src_rect: output rectangle of the plane source in plane fb coordinate
> - * @out_src_x: output src_x of rotator stage in rotator output fb coordinate
> - * @out_src_y: output src y of rotator stage in rotator output fb coordinate
> - * @out_src_w: output src w of rotator stage in rotator output fb ooordinate
> - * @out_src_h: output src h of rotator stage in rotator output fb coordinate
> - * @out_fb_width: output framebuffer width of rotator stage
> - * @out_fb_height: output framebuffer height of rotator stage
> - * @out_fb_pixel_format: output framebuffer pixel format of rotator stage
> - * @out_fb_modifier: output framebuffer modifier of rotator stage
> - * @out_fb_flags: output framebuffer flags of rotator stage
> - * @out_sbuf: true if output streaming buffer is required
> - * @out_fb_format: Pointer to output framebuffer format of rotator stage
> - * @out_fb: Pointer to output drm framebuffer of rotator stage
> - * @out_fbo: framebuffer object of output streaming buffer
> - * @out_xpos: relative horizontal position of the plane (0 - leftmost)
> - */
> -struct dpu_plane_rot_state {
> - u32 sequence_id;
> - struct dpu_hw_rot *rot_hw;
> - bool rot90;
> - bool hflip;
> - bool vflip;
> - struct dpu_hw_rot_cmd rot_cmd;
> - int nplane;
> - /* input */
> - struct drm_framebuffer *in_fb;
> - struct drm_rect in_rot_rect;
> - u32 in_rotation;
> - /* output */
> - struct drm_rect out_rot_rect;
> - struct drm_rect out_src_rect;
> - u32 out_rotation;
> - u32 out_src_x;
> - u32 out_src_y;
> - u32 out_src_w;
> - u32 out_src_h;
> - u32 out_fb_width;
> - u32 out_fb_height;
> - u32 out_fb_pixel_format;
> - u64 out_fb_modifier[4];
> - u32 out_fb_flags;
> - bool out_sbuf;
> - const struct dpu_format *out_fb_format;
> - struct drm_framebuffer *out_fb;
> - struct dpu_kms_fbo *out_fbo;
> - int out_xpos;
> -};
> -
> /* dirty bits for update function */
> #define DPU_PLANE_DIRTY_RECTS 0x1
> #define DPU_PLANE_DIRTY_FORMAT 0x2
> @@ -151,10 +88,6 @@ struct dpu_plane_state {
> struct dpu_hw_pixel_ext pixel_ext;
> enum dpu_plane_sclcheck_state scaler_check_state;
>
> - /* @sc_cfg: system_cache configuration */
> - struct dpu_hw_pipe_sc_cfg sc_cfg;
> - struct dpu_plane_rot_state rot;
> -
> struct dpu_hw_pipe_cdp_cfg cdp_cfg;
> };
>
> @@ -200,17 +133,9 @@ struct dpu_multirect_plane_states {
> * @plane: Pointer to DRM plane object
> * @ctl: Pointer to control hardware
> * @flush_sspp: Pointer to sspp flush control word
> - * @flush_rot: Pointer to rotator flush control word
> */
> void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
> - u32 *flush_sspp, u32 *flush_rot);
> -
> -/**
> - * dpu_plane_rot_calc_prefill - calculate rotator start prefill
> - * @plane: Pointer to drm plane
> - * return: prefill time in line
> - */
> -u32 dpu_plane_rot_calc_prefill(struct drm_plane *plane);
> + u32 *flush_sspp);
>
> /**
> * dpu_plane_restore - restore hw state if previously power collapsed
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 3a2612a..1d81b1b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -25,9 +25,6 @@
> #include "dpu_encoder.h"
> #include "dpu_connector.h"
> #include "dpu_hw_dsc.h"
> -#ifdef CONFIG_DRM_MSM_ROTATOR
> -#include "dpu_hw_rot.h"
> -#endif
>
> #define RESERVED_BY_OTHER(h, r) \
> ((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id))
> @@ -259,11 +256,6 @@ static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw)
> case DPU_HW_BLK_DSC:
> dpu_hw_dsc_destroy(hw);
> break;
> -#ifdef CONFIG_DRM_MSM_ROTATOR
> - case DPU_HW_BLK_ROT:
> - dpu_hw_rot_destroy(hw);
> - break;
> -#endif
> case DPU_HW_BLK_SSPP:
> /* SSPPs are not managed by the resource manager */
> case DPU_HW_BLK_TOP:
> @@ -352,11 +344,6 @@ static int _dpu_rm_hw_blk_create(
> case DPU_HW_BLK_DSC:
> hw = dpu_hw_dsc_init(id, mmio, cat);
> break;
> -#ifdef CONFIG_DRM_MSM_ROTATOR
> - case DPU_HW_BLK_ROT:
> - hw = dpu_hw_rot_init(id, mmio, cat);
> - break;
> -#endif
> case DPU_HW_BLK_SSPP:
> /* SSPPs are not managed by the resource manager */
> case DPU_HW_BLK_TOP:
> @@ -510,15 +497,6 @@ int dpu_rm_init(struct dpu_rm *rm,
> }
> }
>
> - for (i = 0; i < cat->rot_count; i++) {
> - rc = _dpu_rm_hw_blk_create(rm, cat, mmio, DPU_HW_BLK_ROT,
> - cat->rot[i].id, &cat->rot[i]);
> - if (rc) {
> - DPU_ERROR("failed: rot hw not available\n");
> - goto fail;
> - }
> - }
> -
> for (i = 0; i < cat->ctl_count; i++) {
> rc = _dpu_rm_hw_blk_create(rm, cat, mmio, DPU_HW_BLK_CTL,
> cat->ctl[i].id, &cat->ctl[i]);
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 8574f30..b56d91d 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -105,15 +105,10 @@ enum msm_mdp_plane_property {
> PLANE_PROP_VALUE_ADJUST,
> PLANE_PROP_CONTRAST_ADJUST,
> PLANE_PROP_EXCL_RECT_V1,
> - PLANE_PROP_ROT_DST_X,
> - PLANE_PROP_ROT_DST_Y,
> - PLANE_PROP_ROT_DST_W,
> - PLANE_PROP_ROT_DST_H,
> PLANE_PROP_PREFILL_SIZE,
> PLANE_PROP_PREFILL_TIME,
>
> /* enum/bitmask properties */
> - PLANE_PROP_ROTATION,
> PLANE_PROP_BLEND_OP,
> PLANE_PROP_SRC_CONFIG,
>
> @@ -142,8 +137,6 @@ enum msm_mdp_crtc_property {
> CRTC_PROP_LLCC_IB,
> CRTC_PROP_DRAM_AB,
> CRTC_PROP_DRAM_IB,
> - CRTC_PROP_ROT_PREFILL_BW,
> - CRTC_PROP_ROT_CLK,
> CRTC_PROP_IDLE_TIMEOUT,
> CRTC_PROP_DEST_SCALER,
>
> @@ -661,7 +654,7 @@ struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
> void *msm_gem_get_vaddr(struct drm_gem_object *obj);
> void *msm_gem_get_vaddr_active(struct drm_gem_object *obj);
> void msm_gem_put_vaddr(struct drm_gem_object *obj);
> -int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
> +int msm_gem_madvise(struct drm_gem_object *obj, unsigned int madv);
> int msm_gem_sync_object(struct drm_gem_object *obj,
> struct msm_fence_context *fctx, bool exclusive);
> void msm_gem_move_to_active(struct drm_gem_object *obj,
> @@ -700,7 +693,7 @@ struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
> struct drm_gem_object **bos);
> struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
> struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
> -struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
> +struct drm_framebuffer *msm_alloc_stolen_fb(struct drm_device *dev,
> int w, int h, int p, uint32_t format);
>
> struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
Sean Paul, Software Engineer, Google / Chromium OS
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