[Freedreno] [PATCH] rnndb: a6xx: Add kernel registers for the GPU and GMU

[Jordan Crouse]

On Wed, Jan 31, 2018 at 11:06:45AM -0700, Jordan Crouse wrote:
> +	<reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS">
> +		<bitfield name="SPTPRAC_GDSC_POWERING_OFF" pos="0"/>
> +		<bitfield name="SPTPRAC_GDSC_POWERING_ON" pos="1"/>
> +		<bitfield name="SPTPRAC_GDSC_POWER_ON" pos="2"/>
> +		<bitfield name="SPTPRAC_GDSC_POWER_OFF" pos="3"/>

Rob, when you push this, could you invert these two fields?  OFF should be bit 2
and ON should be bit 3.  This will save me from having to go through the hoops
to push a new rnndb patch.  I've already fixed it up manually in the kernel
header.

Thanks,
Jordan

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