[Freedreno] [PATCH 0/5] Adreno A6xx system cache support
Sharat Masetty
smasetty at codeaurora.org
Fri Mar 23 07:19:46 UTC 2018
Some hardware variants contain a system level cache or the last level
cache(llc). This cache is typically a large block which is shared by multiple
clients on the SOC. GPU uses the system cache to cache both the GPU data
buffers(like textures) as well the SMMU pagetables. This helps with
improved render performance as well as lower power consumption by reducing
the bus traffic to the system memory.
The system cache architecture allows the cache to be split into slices which
then be used by multiple SOC clients. This patch series is an effort to enable
and use two of those slices perallocated for the GPU, one for the GPU data
buffers and another for the GPU SMMU hardware pagetables.
This patchseries depends on the core llcc driver which was submitted to the
mailing list: https://patchwork.kernel.org/patch/10184935/ and SMMU support
for upstream hint which will be posted to the lists soon by Vivek.
Sharat Masetty (5):
drm/msm: rearrange the gpu_rmw() function
arm64:dts:sdm845: Add support for GPU LLCC
drm/msm/adreno: Add registers in the GPU CX domain
drm/msm: Pass mmu features to generic layers
drm/msm/A6xx: Add support for using system cache(llc)
arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 +-
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +-
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 4 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 162 +++++++++++++++++++++++++++++++-
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 4 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +-
drivers/gpu/drm/msm/msm_drv.c | 8 ++
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gpu.c | 6 +-
drivers/gpu/drm/msm/msm_gpu.h | 6 +-
drivers/gpu/drm/msm/msm_iommu.c | 13 +++
drivers/gpu/drm/msm/msm_mmu.h | 16 ++++
15 files changed, 231 insertions(+), 14 deletions(-)
--
1.9.1
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