[Freedreno] [DPU PATCH 05/11] drm/msm/dpu: update dpu sub-block offsets wrt dpu base address
Sean Paul
seanpaul at chromium.org
Thu May 10 15:02:25 UTC 2018
On Thu, May 10, 2018 at 01:59:39PM +0530, Rajesh Yadav wrote:
> The dpu sub-block offsets were defined wrt mdss base address
> instead of dpu base address.
> Since, dpu is now defined as a separate device, update hw catalog
> offsets for all dpu sub blocks wrt dpu base address.
>
> Signed-off-by: Rajesh Yadav <ryadav at codeaurora.org>
Reviewed-by: Sean Paul <seanpaul at chromium.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 68 +++++++++++------------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 +++---
> 2 files changed, 43 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index c5b370f..2fd3254 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -80,7 +80,7 @@
> static struct dpu_mdp_cfg sdm845_mdp[] = {
> {
> .name = "top_0", .id = MDP_TOP,
> - .base = 0x1000, .len = 0x45C,
> + .base = 0x0, .len = 0x45C,
> .features = 0,
> .highest_bank_bit = 0x2,
> .has_dest_scaler = true,
> @@ -111,27 +111,27 @@
> static struct dpu_ctl_cfg sdm845_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> - .base = 0x2000, .len = 0xE4,
> + .base = 0x1000, .len = 0xE4,
> .features = BIT(DPU_CTL_SPLIT_DISPLAY)
> },
> {
> .name = "ctl_1", .id = CTL_1,
> - .base = 0x2200, .len = 0xE4,
> + .base = 0x1200, .len = 0xE4,
> .features = BIT(DPU_CTL_SPLIT_DISPLAY)
> },
> {
> .name = "ctl_2", .id = CTL_2,
> - .base = 0x2400, .len = 0xE4,
> + .base = 0x1400, .len = 0xE4,
> .features = 0
> },
> {
> .name = "ctl_3", .id = CTL_3,
> - .base = 0x2600, .len = 0xE4,
> + .base = 0x1600, .len = 0xE4,
> .features = 0
> },
> {
> .name = "ctl_4", .id = CTL_4,
> - .base = 0x2800, .len = 0xE4,
> + .base = 0x1800, .len = 0xE4,
> .features = 0
> },
> };
> @@ -211,21 +211,21 @@
> }
>
> static struct dpu_sspp_cfg sdm845_sspp[] = {
> - SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x5000,
> + SSPP_VIG_BLK("sspp_0", SSPP_VIG0, 0x4000,
> sdm845_vig_sblk_0, 0, DPU_CLK_CTRL_VIG0),
> - SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x7000,
> + SSPP_VIG_BLK("sspp_1", SSPP_VIG1, 0x6000,
> sdm845_vig_sblk_1, 4, DPU_CLK_CTRL_VIG1),
> - SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x9000,
> + SSPP_VIG_BLK("sspp_2", SSPP_VIG2, 0x8000,
> sdm845_vig_sblk_2, 8, DPU_CLK_CTRL_VIG2),
> - SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xb000,
> + SSPP_VIG_BLK("sspp_3", SSPP_VIG3, 0xa000,
> sdm845_vig_sblk_3, 12, DPU_CLK_CTRL_VIG3),
> - SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x25000,
> + SSPP_DMA_BLK("sspp_8", SSPP_DMA0, 0x24000,
> sdm845_dma_sblk_0, 1, DPU_CLK_CTRL_DMA0),
> - SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x27000,
> + SSPP_DMA_BLK("sspp_9", SSPP_DMA1, 0x26000,
> sdm845_dma_sblk_1, 5, DPU_CLK_CTRL_DMA1),
> - SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x29000,
> + SSPP_DMA_BLK("sspp_10", SSPP_DMA2, 0x28000,
> sdm845_dma_sblk_2, 9, DPU_CLK_CTRL_CURSOR0),
> - SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2b000,
> + SSPP_DMA_BLK("sspp_11", SSPP_DMA3, 0x2a000,
> sdm845_dma_sblk_3, 13, DPU_CLK_CTRL_CURSOR1),
> };
>
> @@ -252,17 +252,17 @@
> .lm_pair_mask = (1 << _lmpair) \
> }
> static struct dpu_lm_cfg sdm845_lm[] = {
> - LM_BLK("lm_0", LM_0, 0x45000, DSPP_0,
> + LM_BLK("lm_0", LM_0, 0x44000, DSPP_0,
> DS_0, PINGPONG_0, LM_1),
> - LM_BLK("lm_1", LM_1, 0x46000, DSPP_1,
> + LM_BLK("lm_1", LM_1, 0x45000, DSPP_1,
> DS_1, PINGPONG_1, LM_0),
> - LM_BLK("lm_2", LM_2, 0x47000, DSPP_2,
> + LM_BLK("lm_2", LM_2, 0x46000, DSPP_2,
> DS_MAX, PINGPONG_2, LM_5),
> LM_BLK("lm_3", LM_3, 0x0, DSPP_MAX,
> DS_MAX, PINGPONG_MAX, 0),
> LM_BLK("lm_4", LM_4, 0x0, DSPP_MAX,
> DS_MAX, PINGPONG_MAX, 0),
> - LM_BLK("lm_5", LM_5, 0x4a000, DSPP_3,
> + LM_BLK("lm_5", LM_5, 0x49000, DSPP_3,
> DS_MAX, PINGPONG_3, LM_2),
> };
>
> @@ -270,7 +270,7 @@
> * DSPP sub blocks config
> *************************************************************/
> static struct dpu_dspp_top_cfg sdm845_dspp_top = {
> - .name = "dspp_top", .base = 0x1300, .len = 0xc
> + .name = "dspp_top", .base = 0x300, .len = 0xc
> };
>
> static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
> @@ -304,10 +304,10 @@
> }
>
> static struct dpu_dspp_cfg sdm845_dspp[] = {
> - DSPP_BLK("dspp_0", DSPP_0, 0x55000),
> - DSPP_BLK("dspp_1", DSPP_1, 0x57000),
> - DSPP_BLK("dspp_2", DSPP_2, 0x59000),
> - DSPP_BLK("dspp_3", DSPP_3, 0x5b000),
> + DSPP_BLK("dspp_0", DSPP_0, 0x54000),
> + DSPP_BLK("dspp_1", DSPP_1, 0x56000),
> + DSPP_BLK("dspp_2", DSPP_2, 0x58000),
> + DSPP_BLK("dspp_3", DSPP_3, 0x5a000),
> };
>
> /*************************************************************
> @@ -315,7 +315,7 @@
> *************************************************************/
> static const struct dpu_ds_top_cfg sdm845_ds_top = {
> .name = "ds_top_0", .id = DS_TOP,
> - .base = 0x61000, .len = 0xc,
> + .base = 0x60000, .len = 0xc,
> .maxinputwidth = DEFAULT_DPU_LINE_WIDTH,
> .maxoutputwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
> .maxupscale = MAX_UPSCALE_RATIO,
> @@ -365,10 +365,10 @@
> }
>
> static struct dpu_pingpong_cfg sdm845_pp[] = {
> - PP_BLK_TE("pingpong_0", PINGPONG_0, 0x71000),
> - PP_BLK_TE("pingpong_1", PINGPONG_1, 0x71800),
> - PP_BLK("pingpong_2", PINGPONG_2, 0x72000),
> - PP_BLK("pingpong_3", PINGPONG_3, 0x72800),
> + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000),
> + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800),
> + PP_BLK("pingpong_2", PINGPONG_2, 0x71000),
> + PP_BLK("pingpong_3", PINGPONG_3, 0x71800),
> };
>
> /*************************************************************
> @@ -384,10 +384,10 @@
> }
>
> static struct dpu_intf_cfg sdm845_intf[] = {
> - INTF_BLK("intf_0", INTF_0, 0x6B000, INTF_DP, 0),
> - INTF_BLK("intf_1", INTF_1, 0x6B800, INTF_DSI, 0),
> - INTF_BLK("intf_2", INTF_2, 0x6C000, INTF_DSI, 1),
> - INTF_BLK("intf_3", INTF_3, 0x6C800, INTF_DP, 1),
> + INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0),
> + INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0),
> + INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1),
> + INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1),
> };
>
> /*************************************************************
> @@ -401,7 +401,7 @@
> static struct dpu_wb_cfg sdm845_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> - .base = 0x66000, .len = 0x2c8,
> + .base = 0x65000, .len = 0x2c8,
> .features = WB2_SDM845_MASK,
> .sblk = &sdm845_wb2_sblk,
> .format_list = wb2_formats,
> @@ -414,7 +414,7 @@
> static struct dpu_cdm_cfg sdm845_cdm[] = {
> {
> .name = "cdm_0", .id = CDM_0,
> - .base = 0x7A200, .len = 0x224,
> + .base = 0x79200, .len = 0x224,
> .features = 0,
> .intf_connect = BIT(INTF_3),
> .wb_connect = BIT(WB_2)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index 7093ba4..2de13e3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -20,16 +20,16 @@
>
> /**
> * Register offsets in MDSS register file for the interrupt registers
> - * w.r.t. to the MDSS base
> + * w.r.t. to the MDP base
> */
> -#define MDP_SSPP_TOP0_OFF 0x1000
> -#define MDP_INTF_0_OFF 0x6B000
> -#define MDP_INTF_1_OFF 0x6B800
> -#define MDP_INTF_2_OFF 0x6C000
> -#define MDP_INTF_3_OFF 0x6C800
> -#define MDP_INTF_4_OFF 0x6D000
> -#define MDP_AD4_0_OFF 0x7D000
> -#define MDP_AD4_1_OFF 0x7E000
> +#define MDP_SSPP_TOP0_OFF 0x0
> +#define MDP_INTF_0_OFF 0x6A000
> +#define MDP_INTF_1_OFF 0x6A800
> +#define MDP_INTF_2_OFF 0x6B000
> +#define MDP_INTF_3_OFF 0x6B800
> +#define MDP_INTF_4_OFF 0x6C000
> +#define MDP_AD4_0_OFF 0x7C000
> +#define MDP_AD4_1_OFF 0x7D000
> #define MDP_AD4_INTR_EN_OFF 0x41c
> #define MDP_AD4_INTR_CLEAR_OFF 0x424
> #define MDP_AD4_INTR_STATUS_OFF 0x420
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
--
Sean Paul, Software Engineer, Google / Chromium OS
More information about the Freedreno
mailing list