[Freedreno] [PATCH v16 4/5] dt-bindings: arm-smmu: Add bindings for qcom, smmu-v2

[Vivek Gautam]

Hi Rob,

On Thu, Aug 30, 2018 at 8:16 PM Vivek Gautam
<vivek.gautam at codeaurora.org> wrote:
>
> Add bindings doc for Qcom's smmu-v2 implementation.
>
> Signed-off-by: Vivek Gautam <vivek.gautam at codeaurora.org>
> Reviewed-by: Tomasz Figa <tfiga at chromium.org>
> Tested-by: Srinivas Kandagatla <srinivas.kandagatla at linaro.org>
> ---

I removed your reviewed-by for this particular patch.
Can you please consider giving your review if you find the changes okay now.
Thanks.

Best regards
Vivek

>  .../devicetree/bindings/iommu/arm,smmu.txt         | 39 ++++++++++++++++++++++
>  1 file changed, 39 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> index 8a6ffce12af5..a6504b37cc21 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> @@ -17,10 +17,16 @@ conditions.
>                          "arm,mmu-401"
>                          "arm,mmu-500"
>                          "cavium,smmu-v2"
> +                        "qcom,smmu-v2"
>
>                    depending on the particular implementation and/or the
>                    version of the architecture implemented.
>
> +                  Qcom SoCs must contain, as below, SoC-specific compatibles
> +                  along with "qcom,smmu-v2":
> +                  "qcom,msm8996-smmu-v2", "qcom,smmu-v2",
> +                  "qcom,sdm845-smmu-v2", "qcom,smmu-v2".
> +
>  - reg           : Base address and size of the SMMU.
>
>  - #global-interrupts : The number of global interrupts exposed by the
> @@ -71,6 +77,22 @@ conditions.
>                    or using stream matching with #iommu-cells = <2>, and
>                    may be ignored if present in such cases.
>
> +- clock-names:    List of the names of clocks input to the device. The
> +                  required list depends on particular implementation and
> +                  is as follows:
> +                  - for "qcom,smmu-v2":
> +                    - "bus": clock required for downstream bus access and
> +                             for the smmu ptw,
> +                    - "iface": clock required to access smmu's registers
> +                               through the TCU's programming interface.
> +                  - unspecified for other implementations.
> +
> +- clocks:         Specifiers for all clocks listed in the clock-names property,
> +                  as per generic clock bindings.
> +
> +- power-domains:  Specifiers for power domains required to be powered on for
> +                  the SMMU to operate, as per generic power domain bindings.
> +
>  ** Deprecated properties:
>
>  - mmu-masters (deprecated in favour of the generic "iommus" binding) :
> @@ -137,3 +159,20 @@ conditions.
>                  iommu-map = <0 &smmu3 0 0x400>;
>                  ...
>          };
> +
> +       /* Qcom's arm,smmu-v2 implementation */
> +       smmu4: iommu at d00000 {
> +               compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
> +               reg = <0xd00000 0x10000>;
> +
> +               #global-interrupts = <1>;
> +               interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
> +               #iommu-cells = <1>;
> +               power-domains = <&mmcc MDSS_GDSC>;
> +
> +               clocks = <&mmcc SMMU_MDP_AXI_CLK>,
> +                        <&mmcc SMMU_MDP_AHB_CLK>;
> +               clock-names = "bus", "iface";
> +       };
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
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