[Freedreno] [Mesa-dev] [RFC 2/4] nir: Add a new ALU nir_op_imad

[Eduardo Lima Mitev]

On 1/25/19 5:01 PM, Ilia Mirkin wrote:
> On Fri, Jan 25, 2019 at 10:58 AM Ilia Mirkin <imirkin at alum.mit.edu> wrote:
>>
>> IMAD_S24 isn't src0 * src1 + src2 though. I think this could be called
>> imad24, which I suspect exits on many GPUs (nv50-era NVIDIA definitely
>> had this, and I think maxwell+ has a variant of this implemented by
>> XMAD):
>>
>> (src0 * src1) & 0xffffff + src2
> 
> And of course even that's wrong... the 24th bit has to get
> sign-extended on that. Can express it with shifts.
>

IMAD_S24 is what is currently used in
ir3_compiler_nir::get_image_offset(), so the pass doesn't change
anything regarding computations.

I agree that the nir opcode should hint at the bit limit, so probably
nir_op_imad24. That is one of the open questions.

Thanks,

Eduardo