[Freedreno] [PATCH] dt-bindings: arm-smmu: update the list of clocks

[Sharat Masetty]

On 2/26/2020 8:03 PM, Rob Herring wrote:
> On Wed, Feb 26, 2020 at 5:17 AM Sharat Masetty <smasetty at codeaurora.org> wrote:
>>
>> On 2/21/2020 2:05 AM, Rob Herring wrote:
>>> On Thu, 20 Feb 2020 13:42:22 +0530, Sharat Masetty wrote:
>>>> This patch adds a clock definition needed for powering on the GPU TBUs
>>>> and the GPU TCU.
>>>>
>>>> Signed-off-by: Sharat Masetty <smasetty at codeaurora.org>
>>>> ---
>>>>    Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
>>>>    1 file changed, 3 insertions(+)
>>>>
>>> My bot found errors running 'make dt_binding_check' on your patch:
>>>
>>> Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node
>>> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/iommu/arm,smmu.example.dt.yaml: iommu at d00000: clock-names: ['bus', 'iface'] is too short
>>> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/iommu/arm,smmu.example.dt.yaml: iommu at d00000: clocks: [[4294967295, 123], [4294967295, 124]] is too short
>>>
>>> See https://patchwork.ozlabs.org/patch/1241297
>>> Please check and re-submit.
>> Hi Rob, These issues seem to be from the original code and not related
>> to my patch. Are these going to be blocking errors?
> There are no errors in this binding in mainline. You've added a 3rd
> clock when all the existing users have exactly 2 clocks.

Rob,

Adding something like the following seems to be solving the bot errors, 
but I am not certain if this is the right way to address this issue. Can 
you please comment?

    clock-names:
+    minItems: 2
+    maxItems: 3
      items:
        - const: bus
        - const: iface
+      - const: mem_iface_clk

    clocks:
+    minItems: 2
+    maxItems: 3
      items:
        - description: bus clock required for downstream bus access and 
for the
            smmu ptw
        - description: interface clock required to access smmu's registers
            through the TCU's programming interface.
+      - description: core clock required for the GPU SMMU TBUs and the 
GPU TCU.

>
> Rob
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