[Freedreno] [PATCH 5/5] dt-bindings: drm/msm/gpu: Document OPP phandle list for the GPU

[Sharat Masetty]

Update the documentation for listing the multiple optional GPU and the
DDR OPP tables to help enable DDR scaling.

Signed-off-by: Sharat Masetty <smasetty at codeaurora.org>
---
 .../devicetree/bindings/display/msm/gpu.txt        | 63 +++++++++++++++++++++-
 1 file changed, 61 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt
index 70025cb..ff3ae1b 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/gpu.txt
@@ -21,7 +21,10 @@ Required properties:
   following devices should not list clocks:
    - qcom,adreno-630.2
 - iommus: optional phandle to an adreno iommu instance
-- operating-points-v2: optional phandle to the OPP operating points
+- operating-points-v2: optional phandles to the OPP operating point tables
+  one for the GPU OPPs and the other for the GPU->DDR OPPs. Note that if
+  multiple OPP tables are specified, the GPU OPP table(considered primary)
+  should be the first in the phandle list.
 - interconnects: optional phandle to an interconnect provider.  See
   ../interconnect/interconnect.txt for details.
 - qcom,gmu: For GMU attached devices a phandle to the GMU device that will
@@ -75,7 +78,7 @@ Example a6xx (with GMU):

 		iommus = <&adreno_smmu 0>;

-		operating-points-v2 = <&gpu_opp_table>;
+		operating-points-v2 = <&gpu_opp_table>, <&gpu_ddr_bw_opp_table>;

 		interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;

@@ -85,5 +88,61 @@ Example a6xx (with GMU):
 			memory-region = <&zap_shader_region>;
 			firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"
 		};
+
+		gpu_opp_table: opp-table {
+			compatible = "operating-points-v2";
+
+			opp-430000000 {
+				opp-hz = /bits/ 64 <430000000>;
+				opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+				required-opps = <&gpu_ddr_bw_opp6>;
+			};
+
+			opp-355000000 {
+				opp-hz = /bits/ 64 <355000000>;
+				opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+				required-opps = <&gpu_ddr_bw_opp4>;
+			};
+
+			opp-267000000 {
+				opp-hz = /bits/ 64 <267000000>;
+				opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+				required-opps = <&gpu_ddr_bw_opp4>;
+			};
+
+			opp-180000000 {
+				opp-hz = /bits/ 64 <180000000>;
+				opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+				required-opps = <&gpu_ddr_bw_opp2>;
+			};
+		};
+
+		gpu_ddr_bw_opp_table: gpu-ddr-bw-opp-table {
+			compatible = "operating-points-v2";
+
+			gpu_ddr_bw_opp1: opp-300000000  {
+				opp-peak-kBps =/bits/ 32 <1200000>;
+			};
+
+			gpu_ddr_bw_opp2: opp-451000000  {
+				opp-peak-kBps =/bits/ 32 <1804000>;
+			};
+
+			gpu_ddr_bw_opp3: opp-547000000  {
+				opp-peak-kBps =/bits/ 32 <2188000>;
+			};
+
+			gpu_ddr_bw_opp4: opp-768000000  {
+				opp-peak-kBps =/bits/ 32 <3072000>;
+			};
+
+			gpu_ddr_bw_opp5: opp-1017000000  {
+				opp-peak-kBps =/bits/ 32 <4068000>;
+			};
+
+			gpu_ddr_bw_opp6: opp-1353000000  {
+				opp-peak-kBps =/bits/ 32 <5412000>;
+			};
+		};
 	};
 };
--
2.7.4