[Freedreno] [PATCH 2/3] arm64: dts: sc7180: add bus clock to mdp node for sc7180 target

[Rob Clark]

On Thu, Sep 10, 2020 at 3:00 PM Bjorn Andersson
<bjorn.andersson at linaro.org> wrote:
>
> On Thu 16 Jul 11:35 UTC 2020, Kalyan Thota wrote:
>
> > From: Krishna Manikandan <mkrishn at codeaurora.org>
> >
> > Move the bus clock to mdp device node,in order
> > to facilitate bus band width scaling on sc7180
> > target.
> >
> > The parent device MDSS will not vote for bus bw,
> > instead the vote will be triggered by mdp device
> > node. Since a minimum vote is required to turn
> > on bus clock, move the clock node to mdp device
> > from where the votes are requested.
> >
> > This patch has dependency on the below series
> > https://patchwork.kernel.org/patch/11468783/
> >
>
> Isn't this dependency on an old revision of patch 3/3 in this series?
>
> Regardless, I don't see either the linked patch or patch 3 merged in
> linux-next, so I presume I should not merge this?

I guess that would be "drm/msm/dpu: add support for clk and bw scaling
for display" on msm-next-staging[1] (about to be msm-next)

[1] https://gitlab.freedesktop.org/drm/msm/-/commits/msm-next-staging


> Regards,
> Bjorn
>
> > Signed-off-by: Krishna Manikandan <mkrishn at codeaurora.org>
> > ---
> >  arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > index 4f2c0d1..31fed6d 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > @@ -1510,10 +1510,9 @@
> >                       power-domains = <&dispcc MDSS_GDSC>;
> >
> >                       clocks = <&gcc GCC_DISP_AHB_CLK>,
> > -                              <&gcc GCC_DISP_HF_AXI_CLK>,
> >                                <&dispcc DISP_CC_MDSS_AHB_CLK>,
> >                                <&dispcc DISP_CC_MDSS_MDP_CLK>;
> > -                     clock-names = "iface", "bus", "ahb", "core";
> > +                     clock-names = "iface", "ahb", "core";
> >
> >                       assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
> >                       assigned-clock-rates = <300000000>;
> > @@ -1539,12 +1538,13 @@
> >                                     <0 0x0aeb0000 0 0x2008>;
> >                               reg-names = "mdp", "vbif";
> >
> > -                             clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > +                             clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> > +                                      <&dispcc DISP_CC_MDSS_AHB_CLK>,
> >                                        <&dispcc DISP_CC_MDSS_ROT_CLK>,
> >                                        <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> >                                        <&dispcc DISP_CC_MDSS_MDP_CLK>,
> >                                        <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> > -                             clock-names = "iface", "rot", "lut", "core",
> > +                             clock-names = "bus", "iface", "rot", "lut", "core",
> >                                             "vsync";
> >                               assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
> >                                                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> > --
> > 1.9.1
> >