[Freedreno] [PATCH] drm/msm/dsi: fix check-before-set in the 7nm dsi_pll code

[Dmitry Baryshkov]

Rob,

Any feedback on this? The patches were sent about two weeks ago.

On Thu, 25 Feb 2021 at 01:47, Dmitry Baryshkov
<dmitry.baryshkov at linaro.org> wrote:
>
> Fix setting min/max DSI PLL rate for the V4.1 7nm DSI PLL (used on
> sm8250). Current code checks for pll->type before it is set (as it is
> set in the msm_dsi_pll_init() after calling device-specific functions.
>
> Cc: Jonathan Marek <jonathan at marek.ca>
> Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> ---
>  drivers/gpu/drm/msm/dsi/pll/dsi_pll.c     | 2 +-
>  drivers/gpu/drm/msm/dsi/pll/dsi_pll.h     | 6 ++++--
>  drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 5 +++--
>  3 files changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c
> index a45fe95aff49..3dc65877fa10 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c
> @@ -163,7 +163,7 @@ struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
>                 break;
>         case MSM_DSI_PHY_7NM:
>         case MSM_DSI_PHY_7NM_V4_1:
> -               pll = msm_dsi_pll_7nm_init(pdev, id);
> +               pll = msm_dsi_pll_7nm_init(pdev, type, id);
>                 break;
>         default:
>                 pll = ERR_PTR(-ENXIO);
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
> index 3405982a092c..bbecb1de5678 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
> @@ -117,10 +117,12 @@ msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
>  }
>  #endif
>  #ifdef CONFIG_DRM_MSM_DSI_7NM_PHY
> -struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id);
> +struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev,
> +                                       enum msm_dsi_phy_type type, int id);
>  #else
>  static inline struct msm_dsi_pll *
> -msm_dsi_pll_7nm_init(struct platform_device *pdev, int id)
> +msm_dsi_pll_7nm_init(struct platform_device *pdev,
> +                                       enum msm_dsi_phy_type type, int id)
>  {
>         return ERR_PTR(-ENODEV);
>  }
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
> index 93bf142e4a4e..c1f6708367ae 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
> @@ -852,7 +852,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm)
>         return ret;
>  }
>
> -struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id)
> +struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev,
> +                                       enum msm_dsi_phy_type type, int id)
>  {
>         struct dsi_pll_7nm *pll_7nm;
>         struct msm_dsi_pll *pll;
> @@ -885,7 +886,7 @@ struct msm_dsi_pll *msm_dsi_pll_7nm_init(struct platform_device *pdev, int id)
>         pll = &pll_7nm->base;
>         pll->min_rate = 1000000000UL;
>         pll->max_rate = 3500000000UL;
> -       if (pll->type == MSM_DSI_PHY_7NM_V4_1) {
> +       if (type == MSM_DSI_PHY_7NM_V4_1) {
>                 pll->min_rate = 600000000UL;
>                 pll->max_rate = (unsigned long)5000000000ULL;
>                 /* workaround for max rate overflowing on 32-bit builds: */
> --
> 2.30.0
>


-- 
With best wishes
Dmitry