[Freedreno] [PATCH 21/21] drm/msm/dpu: call hw_intr ops directly

[kernel test robot]

Hi Dmitry,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v5.12-rc4 next-20210324]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Dmitry-Baryshkov/drm-msm-dpu-cleanup-callbacks-resource-manager/20210324-230347
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 7acac4b3196caee5e21fb5ea53f8bc124e6a16fc
config: arm-defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/8f82b58643355f9e0d03c022b66e276c252e633a
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Dmitry-Baryshkov/drm-msm-dpu-cleanup-callbacks-resource-manager/20210324-230347
        git checkout 8f82b58643355f9e0d03c022b66e276c252e633a
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:889:5: warning: no previous prototype for 'dpu_hw_intr_disable_irq_nolock' [-Wmissing-prototypes]
     889 | int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
         |     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


vim +/dpu_hw_intr_disable_irq_nolock +889 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

   888	
 > 889	int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
   890	{
   891		int reg_idx;
   892		const struct dpu_intr_reg *reg;
   893		const struct dpu_irq_type *irq;
   894		const char *dbgstr = NULL;
   895		uint32_t cache_irq_mask;
   896	
   897		if (!intr)
   898			return -EINVAL;
   899	
   900		if (irq_idx < 0 || irq_idx >= ARRAY_SIZE(dpu_irq_map)) {
   901			pr_err("invalid IRQ index: [%d]\n", irq_idx);
   902			return -EINVAL;
   903		}
   904	
   905		irq = &dpu_irq_map[irq_idx];
   906		reg_idx = irq->reg_idx;
   907		reg = &dpu_intr_set[reg_idx];
   908	
   909		cache_irq_mask = intr->cache_irq_mask[reg_idx];
   910		if ((cache_irq_mask & irq->irq_mask) == 0) {
   911			dbgstr = "DPU IRQ is already cleared:";
   912		} else {
   913			dbgstr = "DPU IRQ mask disable:";
   914	
   915			cache_irq_mask &= ~irq->irq_mask;
   916			/* Disable interrupts based on the new mask */
   917			DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask);
   918			/* Cleaning any pending interrupt */
   919			DPU_REG_WRITE(&intr->hw, reg->clr_off, irq->irq_mask);
   920	
   921			/* ensure register write goes through */
   922			wmb();
   923	
   924			intr->cache_irq_mask[reg_idx] = cache_irq_mask;
   925		}
   926	
   927		pr_debug("%s MASK:0x%.8x, CACHE-MASK:0x%.8x\n", dbgstr,
   928				irq->irq_mask, cache_irq_mask);
   929	
   930		return 0;
   931	}
   932	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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