[Freedreno] [PATCH v3 0/3] drm/msm/dpu: simplify RM code
Dmitry Baryshkov
dmitry.baryshkov at linaro.org
Fri Nov 26 02:26:39 UTC 2021
INTF blocks are not really handled by resource manager, they are
assigned at dpu_encoder_setup_display using dpu_encoder_get_intf().
Then this allocation is passed to RM and then returned to then
dpu_encoder. So allocate them outside of RM and use them directly.
While we are at fix, drop the lm_max_width from the RM and fix the
indexing of VBIF in the dpu_kms.
Changes since v2:
- Dropped DSPP, PP and MERGE_3D patches for now.
Changes since v1:
- Split into separate patch series to ease review.
The following changes since commit e4840d537c2c6b1189d4de16ee0f4820e069dcea:
drm/msm: Do hw_init() before capturing GPU state (2021-11-22 10:45:55 -0800)
are available in the Git repository at:
https://git.linaro.org/people/dmitry.baryshkov/kernel.git dpu-rm-clean-3
for you to fetch changes up to 3ad9c16d1c1e010abe72ff943f8de25b64968789:
drm/msm/dpu: drop unused lm_max_width from RM (2021-11-25 11:47:40 +0300)
----------------------------------------------------------------
Dmitry Baryshkov (3):
drm/msm/dpu: consistently index dpu_kms->hw_vbif
drm/msm/dpu: get INTF blocks directly rather than through RM
drm/msm/dpu: drop unused lm_max_width from RM
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 36 +------
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 16 ----
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 5 -
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 8 --
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 8 --
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 26 +++++-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 104 ---------------------
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 6 --
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 8 +-
10 files changed, 32 insertions(+), 187 deletions(-)
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