[Freedreno] [PATCH v4 24/24] drm/exynos: dsi: Adjust probe order

[Maxime Ripard]

Hi Marek,

On Fri, Sep 17, 2021 at 02:35:05PM +0200, Marek Szyprowski wrote:
> Hi,
> 
> On 13.09.2021 12:30, Andrzej Hajda wrote:
> > W dniu 10.09.2021 o 12:12, Maxime Ripard pisze:
> >> Without proper care and an agreement between how DSI hosts and devices
> >> drivers register their MIPI-DSI entities and potential components, we can
> >> end up in a situation where the drivers can never probe.
> >>
> >> Most drivers were taking evasive maneuvers to try to workaround this,
> >> but not all of them were following the same conventions, resulting in
> >> various incompatibilities between DSI hosts and devices.
> >>
> >> Now that we have a sequence agreed upon and documented, let's convert
> >> exynos to it.
> >>
> >> Signed-off-by: Maxime Ripard <maxime at cerno.tech>
> > This patch should be dropped, as it will probably break the driver.
> >
> > Exynos is already compatible with the pattern
> > register-bus-then-get-sink, but it adds/removes panel/bridge
> > dynamically, so it creates drm_device without waiting for downstream sink.
> 
> Right, this patch breaks Exynos DSI driver operation. Without it, the 
> whole series works fine on all Exynos based test boards.

Thanks for testing. Did you have any board using one of those bridges in
your test sample?

Thanks!
Maxime
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