[Freedreno] [PATCH 03/12] drm/msm/dpu: add writeback blocks to DPU RM
Abhinav Kumar
quic_abhinavk at quicinc.com
Thu Apr 14 21:30:13 UTC 2022
On 2/4/2022 3:43 PM, Dmitry Baryshkov wrote:
> On 05/02/2022 00:17, Abhinav Kumar wrote:
>> Add writeback blocks to DPU resource manager so that
>> writeback encoders can request for writeback hardware blocks
>> through RM and their usage can be tracked.
>>
>> Signed-off-by: Abhinav Kumar <quic_abhinavk at quicinc.com>
>
> [please excuse me for the duplicate, I've sent the email without the
> proper distribution list]
>
> We have WB blocks being allocated manually. Could you please consider
> following the ideas from
> https://patchwork.freedesktop.org/patch/470394/?series=99175&rev=1 ?
>
> I think it simplifies the code and shows exact correspondence between WB
> and dpu_encoder.
Yes, will rebase on the latest msm-next which i think already has this
change and refactor this.
>
>> ---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 3 ++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 2 +
>> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 71
>> +++++++++++++++++++++++++++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 +
>> 4 files changed, 78 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>> index e241914..cc10436 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>> @@ -1,5 +1,6 @@
>> /* SPDX-License-Identifier: GPL-2.0-only */
>> /*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
>> * Copyright (C) 2013 Red Hat
>> * Author: Rob Clark <robdclark at gmail.com>
>> @@ -21,9 +22,11 @@
>> /**
>> * Encoder functions and data types
>> * @intfs: Interfaces this encoder is using, INTF_MODE_NONE if
>> unused
>> + * @wbs: Writeback blocks this encoder is using
>> */
>> struct dpu_encoder_hw_resources {
>> enum dpu_intf_mode intfs[INTF_MAX];
>> + enum dpu_intf_mode wbs[WB_MAX];
>> };
>> /**
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
>> index 2d385b4..1e00804 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
>> @@ -1,5 +1,6 @@
>> /* SPDX-License-Identifier: GPL-2.0-only */
>> /*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
>> * Copyright (C) 2013 Red Hat
>> * Author: Rob Clark <robdclark at gmail.com>
>> @@ -146,6 +147,7 @@ struct dpu_global_state {
>> uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];
>> uint32_t intf_to_enc_id[INTF_MAX - INTF_0];
>> uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];
>> + uint32_t wb_to_enc_id[WB_MAX - WB_0];
>> };
>> struct dpu_global_state
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> index f9c83d6..edd0b7a 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
>> @@ -1,5 +1,6 @@
>> // SPDX-License-Identifier: GPL-2.0-only
>> /*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
>> */
>> @@ -9,6 +10,7 @@
>> #include "dpu_hw_ctl.h"
>> #include "dpu_hw_pingpong.h"
>> #include "dpu_hw_intf.h"
>> +#include "dpu_hw_wb.h"
>> #include "dpu_hw_dspp.h"
>> #include "dpu_hw_merge3d.h"
>> #include "dpu_encoder.h"
>> @@ -75,6 +77,14 @@ int dpu_rm_destroy(struct dpu_rm *rm)
>> dpu_hw_intf_destroy(hw);
>> }
>> }
>> + for (i = 0; i < ARRAY_SIZE(rm->wb_blks); i++) {
>> + struct dpu_hw_wb *hw;
>> +
>> + if (rm->wb_blks[i]) {
>> + hw = to_dpu_hw_wb(rm->wb_blks[i]);
>> + dpu_hw_wb_destroy(hw);
>> + }
>> + }
>> return 0;
>> }
>> @@ -187,6 +197,24 @@ int dpu_rm_init(struct dpu_rm *rm,
>> rm->intf_blks[intf->id - INTF_0] = &hw->base;
>> }
>> + for (i = 0; i < cat->wb_count; i++) {
>> + struct dpu_hw_wb *hw;
>> + const struct dpu_wb_cfg *wb = &cat->wb[i];
>> +
>> + if (wb->id < WB_0 || wb->id >= WB_MAX) {
>> + DPU_ERROR("skip intf %d with invalid id\n", wb->id);
>> + continue;
>> + }
>> +
>> + hw = dpu_hw_wb_init(wb->id, mmio, cat);
>> + if (IS_ERR_OR_NULL(hw)) {
>> + rc = PTR_ERR(hw);
>> + DPU_ERROR("failed wb object creation: err %d\n", rc);
>> + goto fail;
>> + }
>> + rm->wb_blks[wb->id - WB_0] = &hw->base;
>> + }
>> +
>> for (i = 0; i < cat->ctl_count; i++) {
>> struct dpu_hw_ctl *hw;
>> const struct dpu_ctl_cfg *ctl = &cat->ctl[i];
>> @@ -479,6 +507,33 @@ static int _dpu_rm_reserve_intf(
>> return 0;
>> }
>> +static int _dpu_rm_reserve_wb(
>> + struct dpu_rm *rm,
>> + struct dpu_global_state *global_state,
>> + uint32_t enc_id,
>> + uint32_t id)
>> +{
>> + int idx = id - WB_0;
>> +
>> + if (idx < 0 || idx >= ARRAY_SIZE(rm->wb_blks)) {
>> + DPU_ERROR("invalid intf id: %d", id);
>> + return -EINVAL;
>> + }
>> +
>> + if (!rm->wb_blks[idx]) {
>> + DPU_ERROR("couldn't find wb id %d\n", id);
>> + return -EINVAL;
>> + }
>> +
>> + if (reserved_by_other(global_state->wb_to_enc_id, idx, enc_id)) {
>> + DPU_ERROR("intf id %d already reserved\n", id);
>> + return -ENAVAIL;
>> + }
>> +
>> + global_state->wb_to_enc_id[idx] = enc_id;
>> + return 0;
>> +}
>> +
>> static int _dpu_rm_reserve_intf_related_hw(
>> struct dpu_rm *rm,
>> struct dpu_global_state *global_state,
>> @@ -497,6 +552,15 @@ static int _dpu_rm_reserve_intf_related_hw(
>> return ret;
>> }
>> + for (i = 0; i < ARRAY_SIZE(hw_res->wbs); i++) {
>> + if (hw_res->wbs[i] == INTF_MODE_NONE)
>> + continue;
>> + id = i + WB_0;
>> + ret = _dpu_rm_reserve_wb(rm, global_state, enc_id, id);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> return ret;
>> }
>> @@ -567,6 +631,8 @@ void dpu_rm_release(struct dpu_global_state
>> *global_state,
>> ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id);
>> _dpu_rm_clear_mapping(global_state->intf_to_enc_id,
>> ARRAY_SIZE(global_state->intf_to_enc_id), enc->base.id);
>> + _dpu_rm_clear_mapping(global_state->wb_to_enc_id,
>> + ARRAY_SIZE(global_state->wb_to_enc_id), enc->base.id);
>> }
>> int dpu_rm_reserve(
>> @@ -635,6 +701,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
>> hw_to_enc_id = global_state->intf_to_enc_id;
>> max_blks = ARRAY_SIZE(rm->intf_blks);
>> break;
>> + case DPU_HW_BLK_WB:
>> + hw_blks = rm->wb_blks;
>> + hw_to_enc_id = global_state->wb_to_enc_id;
>> + max_blks = ARRAY_SIZE(rm->wb_blks);
>> + break;
>> case DPU_HW_BLK_DSPP:
>> hw_blks = rm->dspp_blks;
>> hw_to_enc_id = global_state->dspp_to_enc_id;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> index 1f12c8d..a021409 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
>> @@ -1,5 +1,6 @@
>> /* SPDX-License-Identifier: GPL-2.0-only */
>> /*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
>> */
>> @@ -30,6 +31,7 @@ struct dpu_rm {
>> struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0];
>> struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
>> struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
>> + struct dpu_hw_blk *wb_blks[WB_MAX - WB_0];
>> uint32_t lm_max_width;
>> };
>
>
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