[Freedreno] [PATCH v3 2/3] drm/msm/hdmi: make hdmi_phy_8996 OF clk provider

[Abhinav Kumar]

On 7/4/2022 9:11 AM, Dmitry Baryshkov wrote:
> On MSM8996 the HDMI PHY provides the PLL clock to the MMCC. As we are
> preparing to convert the MSM8996 to use DT clocks properties (rather
> than global clock names), register the OF clock provider.
> 
> While we are at it, also change the driver to use clk_parent_data rather
> parent_names to setup a link to the XO clock.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk at quicinc.com>
> ---
>   drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c | 25 +++++++++++++-----------
>   1 file changed, 14 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
> index b06d9d25a189..4dd055416620 100644
> --- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
> +++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
> @@ -691,15 +691,13 @@ static const struct clk_ops hdmi_8996_pll_ops = {
>   	.is_enabled = hdmi_8996_pll_is_enabled,
>   };
>   
> -static const char * const hdmi_pll_parents[] = {
> -	"xo",
> -};
> -
>   static const struct clk_init_data pll_init = {
>   	.name = "hdmipll",
>   	.ops = &hdmi_8996_pll_ops,
> -	.parent_names = hdmi_pll_parents,
> -	.num_parents = ARRAY_SIZE(hdmi_pll_parents),
> +	.parent_data = (const struct clk_parent_data[]){
> +		{ .fw_name = "xo", .name = "xo_board" },
> +	},
> +	.num_parents = 1,
>   	.flags = CLK_IGNORE_UNUSED,
>   };
>   
> @@ -707,8 +705,7 @@ int msm_hdmi_pll_8996_init(struct platform_device *pdev)
>   {
>   	struct device *dev = &pdev->dev;
>   	struct hdmi_pll_8996 *pll;
> -	struct clk *clk;
> -	int i;
> +	int i, ret;
>   
>   	pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
>   	if (!pll)
> @@ -735,10 +732,16 @@ int msm_hdmi_pll_8996_init(struct platform_device *pdev)
>   	}
>   	pll->clk_hw.init = &pll_init;
>   
> -	clk = devm_clk_register(dev, &pll->clk_hw);
> -	if (IS_ERR(clk)) {
> +	ret = devm_clk_hw_register(dev, &pll->clk_hw);
> +	if (ret) {
>   		DRM_DEV_ERROR(dev, "failed to register pll clock\n");
> -		return -EINVAL;
> +		return ret;
> +	}
> +
> +	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &pll->clk_hw);
> +	if (ret) {
> +		DRM_DEV_ERROR(dev, "%s: failed to register clk provider: %d\n", __func__, ret);
> +		return ret;
>   	}
>   
>   	return 0;