[Freedreno] [PATCH v2 2/7] drm/msm/dpu: move VBIF_XINL_QOS_LVL_REMAP size to hw_catalog

[Abhinav Kumar]

On 6/2/2022 6:30 AM, Dmitry Baryshkov wrote:
> Rather than detecting VBIF_XINL_QOS_LVL_REMAP_000 based on the
> hwversion, push the offset to the hw_catalog.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>

This one is fine because sc7180 and sc7280 use sdm845_vbif.

All chipsets listed in the catalog are covered.

Reviewed-by: Abhinav Kumar <quic_abhinavk at quicinc.com>
> ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 ++
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c    | 4 ++--
>   3 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 78c7d987c2ca..cff6fe3a85ac 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -1339,6 +1339,7 @@ static const struct dpu_vbif_cfg msm8998_vbif[] = {
>   	.default_ot_wr_limit = 32,
>   	.features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM),
>   	.xin_halt_timeout = 0x4000,
> +	.qos_rp_remap_size = 0x20,
>   	.dynamic_ot_rd_tbl = {
>   		.count = ARRAY_SIZE(msm8998_ot_rdwr_cfg),
>   		.cfg = msm8998_ot_rdwr_cfg,
> @@ -1366,6 +1367,7 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = {
>   	.base = 0, .len = 0x1040,
>   	.features = BIT(DPU_VBIF_QOS_REMAP),
>   	.xin_halt_timeout = 0x4000,
> +	.qos_rp_remap_size = 0x40,
>   	.qos_rt_tbl = {
>   		.npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
>   		.priority_lvl = sdm845_rt_pri_lvl,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 80bc09b1f1b3..f70de97f492a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -709,6 +709,7 @@ struct dpu_vbif_qos_tbl {
>    * @ot_rd_limit        default OT read limit
>    * @ot_wr_limit        default OT write limit
>    * @xin_halt_timeout   maximum time (in usec) for xin to halt
> + * @qos_rp_remap_size  size of VBIF_XINL_QOS_RP_REMAP register space
>    * @dynamic_ot_rd_tbl  dynamic OT read configuration table
>    * @dynamic_ot_wr_tbl  dynamic OT write configuration table
>    * @qos_rt_tbl         real-time QoS priority table
> @@ -721,6 +722,7 @@ struct dpu_vbif_cfg {
>   	u32 default_ot_rd_limit;
>   	u32 default_ot_wr_limit;
>   	u32 xin_halt_timeout;
> +	u32 qos_rp_remap_size;
>   	struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl;
>   	struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
>   	struct dpu_vbif_qos_tbl qos_rt_tbl;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
> index b757054e1c23..046854c3fbed 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
> @@ -30,7 +30,7 @@
>   #define VBIF_XIN_HALT_CTRL0		0x0200
>   #define VBIF_XIN_HALT_CTRL1		0x0204
>   #define VBIF_XINL_QOS_RP_REMAP_000	0x0550
> -#define VBIF_XINL_QOS_LVL_REMAP_000(v)	(v < DPU_HW_VER_400 ? 0x570 : 0x0590)
> +#define VBIF_XINL_QOS_LVL_REMAP_000(vbif)	(VBIF_XINL_QOS_RP_REMAP_000 + (vbif)->cap->qos_rp_remap_size)
>   
>   static void dpu_hw_clear_errors(struct dpu_hw_vbif *vbif,
>   		u32 *pnd_errors, u32 *src_errors)
> @@ -163,7 +163,7 @@ static void dpu_hw_set_qos_remap(struct dpu_hw_vbif *vbif,
>   
>   	c = &vbif->hw;
>   
> -	reg_lvl = VBIF_XINL_QOS_LVL_REMAP_000(c->hwversion);
> +	reg_lvl = VBIF_XINL_QOS_LVL_REMAP_000(vbif);
>   	reg_high = ((xin_id & 0x8) >> 3) * 4 + (level * 8);
>   	reg_shift = (xin_id & 0x7) * 4;
>