[Freedreno] [PATCH 06/25] drm/msm/dpu: inline dpu_plane_get_ctl_flush

[Abhinav Kumar]

On 2/9/2022 9:25 AM, Dmitry Baryshkov wrote:
> There is no need to keep a separate function for calling into the ctl if
> we already know all the details. Inline this function in the dpu_crtc.c
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk at quicinc.com>
> ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 15 ++++++++-------
>   drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 ------------
>   drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |  9 ---------
>   3 files changed, 8 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 7318bd45637a..5fc338ef3460 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -348,7 +348,6 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
>   	struct dpu_format *format;
>   	struct dpu_hw_ctl *ctl = mixer->lm_ctl;
>   
> -	u32 flush_mask;
>   	uint32_t stage_idx, lm_idx;
>   	int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 };
>   	bool bg_alpha_enable = false;
> @@ -356,6 +355,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
>   
>   	memset(fetch_active, 0, sizeof(fetch_active));
>   	drm_atomic_crtc_for_each_plane(plane, crtc) {
> +		enum dpu_sspp sspp_idx;
> +
>   		state = plane->state;
>   		if (!state)
>   			continue;
> @@ -363,14 +364,14 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
>   		pstate = to_dpu_plane_state(state);
>   		fb = state->fb;
>   
> -		dpu_plane_get_ctl_flush(plane, ctl, &flush_mask);
> -		set_bit(dpu_plane_pipe(plane), fetch_active);
> +		sspp_idx = dpu_plane_pipe(plane);
> +		set_bit(sspp_idx, fetch_active);
>   
>   		DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n",
>   				crtc->base.id,
>   				pstate->stage,
>   				plane->base.id,
> -				dpu_plane_pipe(plane) - SSPP_VIG0,
> +				sspp_idx - SSPP_VIG0,
>   				state->fb ? state->fb->base.id : -1);
>   
>   		format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
> @@ -380,13 +381,13 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
>   
>   		stage_idx = zpos_cnt[pstate->stage]++;
>   		stage_cfg->stage[pstate->stage][stage_idx] =
> -					dpu_plane_pipe(plane);
> +					sspp_idx;
>   		stage_cfg->multirect_index[pstate->stage][stage_idx] =
>   					pstate->multirect_index;
>   
>   		trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
>   					   state, pstate, stage_idx,
> -					   dpu_plane_pipe(plane) - SSPP_VIG0,
> +					   sspp_idx - SSPP_VIG0,
>   					   format->base.pixel_format,
>   					   fb ? fb->modifier : 0);
>   
> @@ -395,7 +396,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
>   			_dpu_crtc_setup_blend_cfg(mixer + lm_idx,
>   						pstate, format);
>   
> -			mixer[lm_idx].flush_mask |= flush_mask;
> +			mixer[lm_idx].flush_mask |= ctl->ops.get_bitmask_sspp(ctl, sspp_idx);
>   
>   			if (bg_alpha_enable && !format->alpha_enable)
>   				mixer[lm_idx].mixer_op_mode = 0;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index 0247ff8a67a2..ca194cd83cd0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -849,18 +849,6 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane)
>   	return 0;
>   }
>   
> -/**
> - * dpu_plane_get_ctl_flush - get control flush for the given plane
> - * @plane: Pointer to drm plane structure
> - * @ctl: Pointer to hardware control driver
> - * @flush_sspp: Pointer to sspp flush control word
> - */
> -void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
> -		u32 *flush_sspp)
> -{
> -	*flush_sspp = ctl->ops.get_bitmask_sspp(ctl, dpu_plane_pipe(plane));
> -}
> -
>   static int dpu_plane_prepare_fb(struct drm_plane *plane,
>   		struct drm_plane_state *new_state)
>   {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> index 42b88b6bc9c2..aa9478b475d4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> @@ -61,15 +61,6 @@ struct dpu_multirect_plane_states {
>    */
>   enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane);
>   
> -/**
> - * dpu_plane_get_ctl_flush - get control flush mask
> - * @plane:   Pointer to DRM plane object
> - * @ctl: Pointer to control hardware
> - * @flush_sspp: Pointer to sspp flush control word
> - */
> -void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl,
> -		u32 *flush_sspp);
> -
>   /**
>    * dpu_plane_flush - final plane operations before commit flush
>    * @plane: Pointer to drm plane structure