[Freedreno] [PATCH 0/5] drm: Fix math issues in MSM DSC implementation
Marijn Suijten
marijn.suijten at somainline.org
Sat Oct 1 19:08:02 UTC 2022
Various removals of complex yet unnecessary math, fixing all uses of
drm_dsc_config::bits_per_pixel to deal with the fact that this field
includes four fractional bits, and finally an approach for dealing with
dsi_host setting negative values in range_bpg_offset, resulting in
overflow inside drm_dsc_pps_payload_pack().
Note that updating the static bpg_offset array to limit the size of
these negative values to 6 bits changes what would be written to the DPU
hardware at register(s) DSC_RANGE_BPG_OFFSET, hence the choice has been
made to cover up for this while packing the value into a smaller field
instead.
Altogether this series is responsible for solving _all_ Display Stream
Compression issues and artifacts on the Sony Tama (sdm845) Akatsuki
smartphone (2880x1440p).
Marijn Suijten (5):
drm/msm/dsi: Remove useless math in DSC calculation
drm/msm/dsi: Remove repeated calculation of slice_per_intf
drm/msm/dsi: Account for DSC's bits_per_pixel having 4 fractional bits
drm/msm/dpu1: Account for DSC's bits_per_pixel having 4 fractional
bits
drm/dsc: Prevent negative BPG offsets from shadowing adjacent
bitfields
drivers/gpu/drm/display/drm_dsc_helper.c | 6 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 11 +-----
drivers/gpu/drm/msm/dsi/dsi_host.c | 45 ++++++++++++++--------
3 files changed, 33 insertions(+), 29 deletions(-)
--
2.37.3
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