[Freedreno] [PATCH v4 0/5] drm/msm/dpu: rework interrupt handling

[Dmitry Baryshkov]

On Thu, 27 Jul 2023 17:45:38 +0300, Dmitry Baryshkov wrote:
> Please exuse me for the spam, I missed the triggered WARN_ON because of
> the dropped patch.
> 
> Declaring the mask of supported interrupts proved to be error-prone. It
> is very easy to add a bit with no corresponding backing block or to miss
> the INTF TE bit. Replace this static configuration with the irq mask
> calculated from the HW catalog data.
> 
> [...]

Applied, thanks!

[1/5] drm/msm/dpu: inline __intr_offset
      https://gitlab.freedesktop.org/lumag/msm/-/commit/c54b4c35194e
[2/5] drm/msm/dpu: split interrupt address arrays
      https://gitlab.freedesktop.org/lumag/msm/-/commit/370891f0d983
[3/5] drm/msm/dpu: autodetect supported interrupts
      https://gitlab.freedesktop.org/lumag/msm/-/commit/bf8198cc3b90
[4/5] drm/msm/dpu: drop now-unused mdss_irqs field from hw catalog
      https://gitlab.freedesktop.org/lumag/msm/-/commit/40f9cedf54f1
[5/5] drm/msm/dpu: drop compatibility INTR defines
      https://gitlab.freedesktop.org/lumag/msm/-/commit/edb34ac1f65e

Best regards,
-- 
Dmitry Baryshkov <dmitry.baryshkov at linaro.org>