[PATCH 3/3] arm64: dts: qcom: sm8650: Add DisplayPort device nodes

[Neil Armstrong]

On 07/12/2023 20:47, Konrad Dybcio wrote:
> 
> 
> On 12/7/23 17:37, Neil Armstrong wrote:
>> Declare the displayport controller present on the Qualcomm SM8650 SoC
>> and connected to the USB3/DP Combo PHY.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong at linaro.org>
>> ---
> [...]
> 
>> +                clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> +                     <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> +                     <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
>> +                     <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
>> +                     <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> What about PIXEL1 clocks?

PIXEL1 is not defined yet in the bindings, but available since SM8150...

# grep -l PIXEL1 include/dt-bindings/ -R
include/dt-bindings/clock/qcom,dispcc-sm8350.h
include/dt-bindings/clock/qcom,sm8650-dispcc.h
include/dt-bindings/clock/qcom,dispcc-sm8250.h
include/dt-bindings/clock/qcom,sm8450-dispcc.h
include/dt-bindings/clock/qcom,sm8550-dispcc.h
include/dt-bindings/clock/qcom,dispcc-sdm845.h
include/dt-bindings/clock/qcom,dispcc-sm8150.h
include/dt-bindings/clock/qcom,dispcc-sc8280xp.h


> 
> [...]
> 
>> +                    opp-162000000 {
>> +                        opp-hz = /bits/ 64 <162000000>;
>> +                        required-opps = <&rpmhpd_opp_low_svs_d1>;
>> +                    };
>> +
>> +                    opp-270000000 {
>> +                        opp-hz = /bits/ 64 <270000000>;
>> +                        required-opps = <&rpmhpd_opp_low_svs>;
>> +                    };
>> +
>> +                    opp-540000000 {
>> +                        opp-hz = /bits/ 64 <540000000>;
>> +                        required-opps = <&rpmhpd_opp_svs_l1>;
>> +                    };
>> +
>> +                    opp-810000000 {
>> +                        opp-hz = /bits/ 64 <810000000>;
>> +                        required-opps = <&rpmhpd_opp_nom>;
>> +                    };
>> +                };
>> +            };
>>           };
>>           dispcc: clock-controller at af00000 {
>> @@ -2996,8 +3086,8 @@ dispcc: clock-controller at af00000 {
>>                    <&mdss_dsi0_phy 1>,
>>                    <&mdss_dsi1_phy 0>,
>>                    <&mdss_dsi1_phy 1>,
>> -                 <0>, /* dp0 */
>> -                 <0>,
>> +                 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> +                 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>>                    <0>, /* dp1 */
>>                    <0>,
>>                    <0>, /* dp2 */
> I noticed that this is not in line with your mdss patch [1]
> where there are only two DP INTFs available.. Unless all of
> these controllers can work using some sharing/only some at
> one time...

So, yes there's some more eDP PHYs and MDSS Interfaces, like SM8450 and SM8550 BTW,
but they are not used on the current SoC Packages, they will perhaps be used
in SoC variants, but for now there's clock inputs but no physical output
for those DP interfaces so they're ignored, in upstream and downstream.

$ grep -l -E "DPTX[1-3]" include/dt-bindings/clock/qcom,* -R
include/dt-bindings/clock/qcom,sm8450-dispcc.h
include/dt-bindings/clock/qcom,sm8550-dispcc.h
include/dt-bindings/clock/qcom,sm8650-dispcc.h

Neil

> 
> Konrad
> 
> [1] https://lore.kernel.org/all/20231030-topic-sm8650-upstream-mdss-v2-5-43f1887c82b8@linaro.org/