[Freedreno] [PATCH 05/10] drm/msm/dpu: Allow variable SSPP/INTF_BLK size

[Dmitry Baryshkov]

On 13/02/2023 16:31, Marijn Suijten wrote:
> On 2023-02-13 13:38:33, Dmitry Baryshkov wrote:
>> On 13/02/2023 13:12, Marijn Suijten wrote:
>>> On 2023-02-11 13:26:51, Konrad Dybcio wrote:
>>>> These blocks are of variable length on different SoCs. Set the
>>>> correct values where I was able to retrieve it from downstream
>>>> DTs and leave the old defaults (0x1c8 for sspp and 0x280 for
>>>> intf) otherwise.
>>>>
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio at linaro.org>
>>>> ---
>>>>    .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 242 +++++++++---------
>>>>    1 file changed, 121 insertions(+), 121 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>> index 802050118345..d9ef1e133c1e 100644
>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>>> [..]
>>>> @@ -1848,10 +1848,10 @@ static struct dpu_dsc_cfg sm8150_dsc[] = {
>>>>    /*************************************************************
>>>>     * INTF sub blocks config
>>>>     *************************************************************/
>>>> -#define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
>>>> +#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
>>>
>>> Dmitry and I discussed in #freedreno to instead add the INTF_BLK_DSI_TE
>>> macro that accounts for the INTF TE registers using this higher register
>>> area, as well as an extended signature to configure extra interrupts.
>>
>> Yes, that's still the plan. It's slightly painful that we are touching
>> this are simultaneously.
> 
> Should we (Konrad) then drop this patch as there's no need to add these
> (mostly RAZ/WI) registers to the dump until my INTF TE series starts
> using them?  That'll make rebasing easier on everyone too.

RAZ/WI is for not present registers (read-as-zero/write-ignore). I think 
that the growing register space is getting populated with registers 
(which we have been ignoring up to now).

> 
> - Marijn
> 
>>> (Besides, I think the len is currently only used for snapshot dumping
>>> and no validation for out-of-blk reads/writes)
>>
>> Yes. Because in most of the cases non-existing registers seem to be RAZ/WI.
>>
>>>
>>>>    	{\
>>>>    	.name = _name, .id = _id, \
>>>> -	.base = _base, .len = 0x280, \
>>>> +	.base = _base, .len = _len, \
>>>>    	.features = _features, \
>>>>    	.type = _type, \
>>>>    	.controller_id = _ctrl_id, \
>>> [..]
>>>
>>> - Marijn
>>
>> -- 
>> With best wishes
>> Dmitry
>>

-- 
With best wishes
Dmitry