[Freedreno] [PATCH v2 07/14] drm/msm/a6xx: Add support for A619_holi
Dmitry Baryshkov
dmitry.baryshkov at linaro.org
Fri Feb 17 21:19:22 UTC 2023
On 14/02/2023 19:31, Konrad Dybcio wrote:
> A619_holi is a GMU-less variant of the already-supported A619 GPU.
> It's present on at least SM4350 (holi) and SM6375 (blair). No mesa
> changes are required. Add the required kernel-side support for it.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio at linaro.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 37 +++++++++++++++++-----
> drivers/gpu/drm/msm/adreno/adreno_device.c | 13 ++++++++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++
> 3 files changed, 47 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 75cf94b03c29..c168712a0dc4 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -614,14 +614,14 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> return;
>
> /* Disable SP clock before programming HWCG registers */
> - if (!adreno_has_gmu_wrapper(adreno_gpu))
> + if ((!adreno_has_gmu_wrapper(adreno_gpu) || adreno_is_a619_holi(adreno_gpu)))
Extra parenthesis made me interpret this incorrectly. Maybe you can
remove them and spit the condition onto two lines? Because my first
interpretation was:
if (!(has_gmu_wrapper || a619_holi)).
> gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
>
> for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
> gpu_write(gpu, reg->offset, state ? reg->value : 0);
>
> /* Enable SP clock */
> - if (!adreno_has_gmu_wrapper(adreno_gpu))
> + if ((!adreno_has_gmu_wrapper(adreno_gpu) || adreno_is_a619_holi(adreno_gpu)))
> gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
>
> gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
> @@ -1007,7 +1007,12 @@ static int hw_init(struct msm_gpu *gpu)
> }
>
> /* Clear GBIF halt in case GX domain was not collapsed */
> - if (a6xx_has_gbif(adreno_gpu)) {
> + if (adreno_is_a619_holi(adreno_gpu)) {
> + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
> + gpu_write(gpu, 0x18, 0);
> + /* Let's make extra sure that the GPU can access the memory.. */
> + mb();
> + } else if (a6xx_has_gbif(adreno_gpu)) {
> gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
> gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0);
> /* Let's make extra sure that the GPU can access the memory.. */
> @@ -1016,6 +1021,9 @@ static int hw_init(struct msm_gpu *gpu)
>
> gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
>
> + if (adreno_is_a619_holi(adreno_gpu))
> + a6xx_sptprac_enable(gmu);
> +
> /*
> * Disable the trusted memory range - we don't actually supported secure
> * memory rendering at this point in time and we don't want to block off
> @@ -1293,7 +1301,8 @@ static void a6xx_dump(struct msm_gpu *gpu)
> #define GBIF_CLIENT_HALT_MASK BIT(0)
> #define GBIF_ARB_HALT_MASK BIT(1)
> #define VBIF_RESET_ACK_TIMEOUT 100
> -#define VBIF_RESET_ACK_MASK 0x00f0
> +#define VBIF_RESET_ACK_MASK 0xF0
> +#define GPR0_GBIF_HALT_REQUEST 0x1E0
>
> static void a6xx_recover(struct msm_gpu *gpu)
> {
> @@ -1350,10 +1359,16 @@ static void a6xx_recover(struct msm_gpu *gpu)
>
> /* Software-reset the GPU */
> if (adreno_has_gmu_wrapper(adreno_gpu)) {
> - /* Halt the GX side of GBIF */
> - gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK);
> - spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) &
> - GBIF_GX_HALT_MASK);
> + if (adreno_is_a619_holi(adreno_gpu)) {
> + gpu_write(gpu, 0x18, GPR0_GBIF_HALT_REQUEST);
> + spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) &
> + (VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK);
> + } else {
> + /* Halt the GX side of GBIF */
> + gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, GBIF_GX_HALT_MASK);
> + spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) &
> + GBIF_GX_HALT_MASK);
> + }
>
> /* Halt new client requests on GBIF */
> gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
> @@ -1763,6 +1778,9 @@ static int a6xx_pm_resume(struct msm_gpu *gpu)
> if (ret)
> return ret;
>
> + if (adreno_is_a619_holi(adreno_gpu))
> + a6xx_sptprac_enable(gmu);
> +
> mutex_unlock(&a6xx_gpu->gmu.lock);
>
> msm_devfreq_resume(gpu);
> @@ -1795,6 +1813,9 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)
>
> mutex_lock(&a6xx_gpu->gmu.lock);
>
> + if (adreno_is_a619_holi(adreno_gpu))
> + a6xx_sptprac_disable(gmu);
> +
> ret = clk_prepare_enable(gpu->ebi1_clk);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index 82757f005a1a..71faeb3fd466 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -264,6 +264,19 @@ static const struct adreno_info gpulist[] = {
> .gmem = SZ_512K,
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a6xx_gpu_init,
> + }, {
> + .rev = ADRENO_REV(6, 1, 9, 1),
I think this deserves a comment that GMU-enabled sm6350 has patch_id 0
(if I interpreted the vendor dtsi correctly).
Another option might be to actually check for the qcom,gmu presense and
add that to the selection conditional.
> + .revn = 619,
> + .name = "A619_holi",
> + .fw = {
> + [ADRENO_FW_SQE] = "a630_sqe.fw",
> + },
> + .gmem = SZ_512K,
> + .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> + .quirks = ADRENO_QUIRK_GMU_WRAPPER,
> + .init = a6xx_gpu_init,
> + .zapfw = "a615_zap.mdt",
> + .hwcg = a615_hwcg,
> }, {
> .rev = ADRENO_REV(6, 1, 9, ANY_ID),
> .revn = 619,
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 7c5e0a90b5fb..16241368c2e4 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -252,6 +252,11 @@ static inline int adreno_is_a619(struct adreno_gpu *gpu)
> return gpu->revn == 619;
> }
>
> +static inline int adreno_is_a619_holi(struct adreno_gpu *gpu)
> +{
> + return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu);
> +}
> +
> static inline int adreno_is_a630(struct adreno_gpu *gpu)
> {
> return gpu->revn == 630;
--
With best wishes
Dmitry
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