[Freedreno] [PATCH 1/3] drm/msm/dpu: fix blend setup for DMA4 and DMA5 layers
Neil Armstrong
neil.armstrong at linaro.org
Mon Jan 16 15:32:38 UTC 2023
On 16/01/2023 07:33, Dmitry Baryshkov wrote:
> SM8550 uses new register to map SSPP_DMA4 and SSPP_DMA5 units to blend
> stages. Add proper support for this register to allow using these two
> planes for image processing.
>
> Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550")
> Cc: Neil Armstrong <neil.armstrong at linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 15 +++++++++------
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 19 +++++++++++++++++++
> 3 files changed, 30 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 835d6d2c4115..504a22c76412 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -67,6 +67,9 @@
> #define CTL_SC7280_MASK \
> (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG))
>
> +#define CTL_SM8550_MASK \
> + (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
> +
> #define MERGE_3D_SM8150_MASK (0)
>
> #define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC)
> @@ -999,37 +1002,37 @@ static const struct dpu_ctl_cfg sm8550_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x290,
> - .features = CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
> + .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> },
> {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x290,
> - .features = CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
> + .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> },
> {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> + .features = CTL_SM8550_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> },
> {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> + .features = CTL_SM8550_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> },
> {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> + .features = CTL_SM8550_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> },
> {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> + .features = CTL_SM8550_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index a1f18d53db6d..d152fef438f9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -199,6 +199,7 @@ enum {
> * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
> * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs)
> * @DPU_CTL_VM_CFG: CTL config to support multiple VMs
> + * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register
> * @DPU_CTL_MAX
> */
> enum {
> @@ -206,6 +207,7 @@ enum {
> DPU_CTL_ACTIVE_CFG,
> DPU_CTL_FETCH_ACTIVE,
> DPU_CTL_VM_CFG,
> + DPU_CTL_HAS_LAYER_EXT4,
> DPU_CTL_MAX
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index a35ecb6676c8..f4fdf537616c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -17,6 +17,8 @@
> (0x70 + (((lm) - LM_0) * 0x004))
> #define CTL_LAYER_EXT3(lm) \
> (0xA0 + (((lm) - LM_0) * 0x004))
> +#define CTL_LAYER_EXT4(lm) \
> + (0xB8 + (((lm) - LM_0) * 0x004))
> #define CTL_TOP 0x014
> #define CTL_FLUSH 0x018
> #define CTL_START 0x01C
> @@ -383,6 +385,7 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
> struct dpu_hw_blk_reg_map *c = &ctx->hw;
> u32 mixercfg = 0, mixercfg_ext = 0, mix, ext;
> u32 mixercfg_ext2 = 0, mixercfg_ext3 = 0;
> + u32 mixercfg_ext4 = 0;
> int i, j;
> int stages;
> int pipes_per_stage;
> @@ -492,6 +495,20 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
> mixercfg_ext2 |= mix << 4;
> }
> break;
> + case SSPP_DMA4:
> + if (rect_index == DPU_SSPP_RECT_1) {
> + mixercfg_ext4 |= ((i + 1) & 0xF) << 8;
> + } else {
> + mixercfg_ext4 |= ((i + 1) & 0xF) << 0;
> + }
> + break;
> + case SSPP_DMA5:
> + if (rect_index == DPU_SSPP_RECT_1) {
> + mixercfg_ext4 |= ((i + 1) & 0xF) << 12;
> + } else {
> + mixercfg_ext4 |= ((i + 1) & 0xF) << 4;
> + }
> + break;
> case SSPP_CURSOR0:
> mixercfg_ext |= ((i + 1) & 0xF) << 20;
> break;
> @@ -509,6 +526,8 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
> DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext);
> DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2);
> DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg_ext3);
> + if ((test_bit(DPU_CTL_HAS_LAYER_EXT4, &ctx->caps->features)))
> + DPU_REG_WRITE(c, CTL_LAYER_EXT4(lm), mixercfg_ext4);
> }
>
>
Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>
Tested-by: Neil Armstrong <neil.armstrong at linaro.org> # on SM8550
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