[Freedreno] [PATCH Resend v11 12/15] drm/msm/disp/dpu: wait for extra vsync till timing engine status is disabled

[Dmitry Baryshkov]

On 19/01/2023 16:26, Vinod Polimera wrote:
> There can be a race between timing gen disable and vblank irq. The
> wait post timing gen disable may return early but intf disable sequence
> might not be completed. Ensure that, intf status is disabled before
> we retire the function.
> 
> Signed-off-by: Vinod Polimera <quic_vpolimer at quicinc.com>

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>

> ---
>   .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c    | 21 +++++++++++++++++++++
>   1 file changed, 21 insertions(+)

-- 
With best wishes
Dmitry