[Freedreno] [PATCH v2 5/5] drm/msm/dpu: Update dev core dump to dump registers of sub-blocks
Dmitry Baryshkov
dmitry.baryshkov at linaro.org
Wed Jul 5 20:22:40 UTC 2023
On 05/07/2023 22:30, Ryan McCann wrote:
> Currently, the device core dump mechanism does not dump registers of
> sub-blocks within the DSPP, SSPP, DSC, and PINGPONG blocks. Edit
> dpu_kms_mdp_snapshot function to account for sub-blocks.
>
> Signed-off-by: Ryan McCann <quic_rmccann at quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 106 ++++++++++++++++++++++++--------
> 1 file changed, 82 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index aa8499de1b9f..c83f5d79e5c5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -890,62 +890,120 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k
> int i;
> struct dpu_kms *dpu_kms;
> const struct dpu_mdss_cfg *cat;
> + void __iomem *mmio;
> + u32 base;
>
> dpu_kms = to_dpu_kms(kms);
>
> cat = dpu_kms->catalog;
> + mmio = dpu_kms->mmio;
>
> pm_runtime_get_sync(&dpu_kms->pdev->dev);
>
> /* dump CTL sub-blocks HW regs info */
> for (i = 0; i < cat->ctl_count; i++)
> - msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len,
> - dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i);
> + msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len, mmio + cat->ctl[i].base,
> + "%s", cat->ctl[i].name);
This is not relevant to sub-blocks. If you wish to refactor the main
block printing, please split it to a separate commit.
Also, please note that `msm_disp_snapshot_add_block(...., "%s",
block->name)` is redundant. We do not expect formatting characters in
block names. So, "%s" can be dropped.
>
> /* dump DSPP sub-blocks HW regs info */
> - for (i = 0; i < cat->dspp_count; i++)
> - msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len,
> - dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i);
> + for (i = 0; i < cat->dspp_count; i++) {
> + base = cat->dspp[i].base;
> + msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, mmio + base, "%s",
> + cat->dspp[i].name);
> +
> + if (cat->dspp[i].sblk && cat->dspp[i].sblk->pcc.len > 0)
> + msm_disp_snapshot_add_block(disp_state, cat->dspp[i].sblk->pcc.len,
> + mmio + base + cat->dspp[i].sblk->pcc.base,
> + "%s_%s", cat->dspp[i].name,
> + cat->dspp[i].sblk->pcc.name);
> + }
> +
>
> /* dump INTF sub-blocks HW regs info */
> for (i = 0; i < cat->intf_count; i++)
> - msm_disp_snapshot_add_block(disp_state, cat->intf[i].len,
> - dpu_kms->mmio + cat->intf[i].base, "intf_%d", i);
> + msm_disp_snapshot_add_block(disp_state, cat->intf[i].len, mmio + cat->intf[i].base,
> + "%s", cat->intf[i].name);
>
> /* dump PP sub-blocks HW regs info */
> - for (i = 0; i < cat->pingpong_count; i++)
> - msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len,
> - dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i);
> + for (i = 0; i < cat->pingpong_count; i++) {
> + base = cat->pingpong[i].base;
> + msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, mmio + base, "%s",
> + cat->pingpong[i].name);
> +
> + /* TE2 block has length of 0, so will not print it */
> +
> + if (cat->pingpong[i].sblk && cat->pingpong[i].sblk->dither.len > 0)
> + msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].sblk->dither.len,
> + mmio + base + cat->pingpong[i].sblk->dither.base,
> + "%s_%s", cat->pingpong[i].name,
> + cat->pingpong[i].sblk->dither.name);
> + }
>
> /* dump SSPP sub-blocks HW regs info */
> - for (i = 0; i < cat->sspp_count; i++)
> - msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len,
> - dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i);
> + for (i = 0; i < cat->sspp_count; i++) {
> + base = cat->sspp[i].base;
> + msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, mmio + cat->sspp[i].base,
> + "%s", cat->sspp[i].name);
> +
> + if (cat->sspp[i].sblk && cat->sspp[i].sblk->scaler_blk.len > 0)
> + msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->scaler_blk.len,
> + mmio + base + cat->sspp[i].sblk->scaler_blk.base,
> + "%s_%s", cat->sspp[i].name,
> + cat->sspp[i].sblk->scaler_blk.name);
> +
> + if (cat->sspp[i].sblk && cat->sspp[i].sblk->csc_blk.len > 0)
> + msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->csc_blk.len,
> + mmio + base + cat->sspp[i].sblk->csc_blk.base,
> + "%s_%s", cat->sspp[i].name,
> + cat->sspp[i].sblk->csc_blk.name);
> + }
>
> /* dump LM sub-blocks HW regs info */
> for (i = 0; i < cat->mixer_count; i++)
> msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len,
> - dpu_kms->mmio + cat->mixer[i].base, "lm_%d", i);
> + mmio + cat->mixer[i].base,
> + "%s", cat->mixer[i].name);
>
> /* dump WB sub-blocks HW regs info */
> for (i = 0; i < cat->wb_count; i++)
> - msm_disp_snapshot_add_block(disp_state, cat->wb[i].len,
> - dpu_kms->mmio + cat->wb[i].base, "wb_%d", i);
> + msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, mmio + cat->wb[i].base,
> + "%s", cat->wb[i].name);
>
> if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) {
> - msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0,
> - dpu_kms->mmio + cat->mdp[0].base, "top");
> + msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0, mmio + cat->mdp[0].base,
> + "top");
> msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP0_END,
> - dpu_kms->mmio + cat->mdp[0].base + MDP_PERIPH_TOP0_END, "top_2");
> + mmio + cat->mdp[0].base + MDP_PERIPH_TOP0_END,
> + "top_2");
> } else {
> - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
> - dpu_kms->mmio + cat->mdp[0].base, "top");
> + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, mmio + cat->mdp[0].base,
> + "top");
> }
>
> /* dump DSC sub-blocks HW regs info */
> - for (i = 0; i < cat->dsc_count; i++)
> - msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len,
> - dpu_kms->mmio + cat->dsc[i].base, "dsc_%d", i);
> + for (i = 0; i < cat->dsc_count; i++) {
> + base = cat->dsc[i].base;
> +
> + if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) {
> + struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc;
> + struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl;
> +
> + /* For now, pass in a length of 0 because the DSC_BLK register space
> + * overlaps with the sblks' register space.
> + *
> + * TODO: Pass in a length of 0 t0 DSC_BLK_1_2 in the HW catalog where
> + * applicable.
> + */
> + msm_disp_snapshot_add_block(disp_state, 0, mmio + base, "%s", cat->dsc[i].name);
> + msm_disp_snapshot_add_block(disp_state, enc.len, mmio + base + enc.base,
> + "%s_%s", cat->dsc[i].name, enc.name);
> + msm_disp_snapshot_add_block(disp_state, ctl.len, mmio + base + ctl.base,
> + "%s_%s", cat->dsc[i].name, ctl.name);
> + } else {
> + msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, mmio + base, "%s",
> + cat->dsc[i].name);
> + }
> + }
>
> pm_runtime_put_sync(&dpu_kms->pdev->dev);
> }
>
--
With best wishes
Dmitry
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