[Freedreno] (subset) [PATCH v2 0/8] MDSS reg bus interconnect

[Abhinav Kumar]

On Wed, 12 Jul 2023 15:11:37 +0300, Dmitry Baryshkov wrote:
> Per agreement with Konrad, picked up this patch series.
> 
> Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's
> another path that needs to be handled to ensure MDSS functions properly,
> namely the "reg bus", a.k.a the CPU-MDSS interconnect.
> 
> Gating that path may have a variety of effects. from none to otherwise
> inexplicable DSI timeouts.
> 
> [...]

Applied, thanks!

[2/8] drm/msm/mdss: correct UBWC programming for SM8550
      https://gitlab.freedesktop.org/drm/msm/-/commit/a85c238c5ccd

Best regards,
-- 
Abhinav Kumar <quic_abhinavk at quicinc.com>