[Freedreno] [PATCH] drm/msm/dpu: add missing flush and fetch bits for DMA4/DMA5 planes

[Abhinav Kumar]

On Tue, 04 Jul 2023 12:01:04 -0400, Jonathan Marek wrote:
> Note that with this, DMA4/DMA5 are still non-functional, but at least
> display *something* in modetest instead of nothing or underflow.
> 
> 

Applied, thanks!

[1/1] drm/msm/dpu: add missing flush and fetch bits for DMA4/DMA5 planes
      https://gitlab.freedesktop.org/drm/msm/-/commit/ba7a94ea7312

Best regards,
-- 
Abhinav Kumar <quic_abhinavk at quicinc.com>