[Freedreno] [PATCH 2/2] drm/msm/dsi: don't allow enabling 7nm VCO with unprogrammed rate

[Marijn Suijten]

On 2023-06-12 11:15:53, Marijn Suijten wrote:
> On 2023-06-12 06:16:16, Dmitry Baryshkov wrote:
> > CCF can try enabling VCO before the rate has been programmed. This can
> > cause clock lockups and/or other boot issues. Program the VCO to the
> > minimal PLL rate if the read rate is 0 Hz.
> > 
> > Reported-by: Degdag Mohamed <degdagmohamed at gmail.com>
> > Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> 
> This unfortunately regresses my Xperia 5 (sofef01 panel driver that's
> on the lists) to now run at 30~33Hz instead of 60Hz.  I can provide
> debugging and clk trees later, if needed.

I'll also retest the Xperia 1 with this, which has a 4k DSC panel.

Is this intended to get rid of:

    msm_dsi_phy ae94400.phy: [drm:dsi_pll_7nm_vco_prepare] *ERROR* DSI PLL(0) lock failed, status=0x00000000: -110
    PLL(0) lock failed

... at startup (and relevant rcg2 update_config failures, unbalanced
disables etc)?  It locks after a couple tries but it's still
unnecessarily spammy.

- Marijn

> 
> - Marijn
> 
> > ---
> >  drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> > index 3b1ed02f644d..6979d35eb7c3 100644
> > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> > @@ -395,11 +395,16 @@ static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll)
> >  	wmb(); /* Ensure that the reset is deasserted */
> >  }
> >  
> > +static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
> > +						  unsigned long parent_rate);
> >  static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
> >  {
> >  	struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
> >  	int rc;
> >  
> > +	if (dsi_pll_7nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0)
> > +		dsi_pll_7nm_vco_set_rate(hw, pll_7nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE);
> > +
> >  	dsi_pll_enable_pll_bias(pll_7nm);
> >  	if (pll_7nm->slave)
> >  		dsi_pll_enable_pll_bias(pll_7nm->slave);
> > -- 
> > 2.39.2
> >