[Freedreno] [v2,45/50] drm/msm/dpu: inline IRQ_n_MASK defines
Konrad Dybcio
konrad.dybcio at linaro.org
Thu Mar 30 13:08:52 UTC 2023
On 12.02.2023 00:12, Dmitry Baryshkov wrote:
> IRQ masks are rarely shared between different DPU revisions. Inline them
> to the dpu_mdss_cfg intances and drop them from the dpu_hw_catalog.c
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> ---
Everything looks good!
Reviewed-by: Konrad Dybcio <konrad.dybcio at linaro.org>
Konrad
> .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 9 ++-
> .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 10 ++-
> .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 10 ++-
> .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 12 ++-
> .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 9 ++-
> .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 6 +-
> .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 6 +-
> .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 6 +-
> .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 8 +-
> .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +-
> .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 13 +++-
> .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8 +-
> .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 8 +-
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 73 -------------------
> 14 files changed, 99 insertions(+), 86 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index 36a4f11f44b7..1eb3b5a9d485 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -198,7 +198,14 @@ static const struct dpu_mdss_cfg msm8998_dpu_cfg = {
> .vbif = msm8998_vbif,
> .reg_dma_count = 0,
> .perf = &msm8998_perf_data,
> - .mdss_irqs = IRQ_SM8250_MASK,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR) | \
> + BIT(MDP_INTF2_INTR) | \
> + BIT(MDP_INTF3_INTR) | \
> + BIT(MDP_INTF4_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 739a301afcb4..cc6431e42932 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -197,7 +197,15 @@ static const struct dpu_mdss_cfg sdm845_dpu_cfg = {
> .reg_dma_count = 1,
> .dma_cfg = &sdm845_regdma,
> .perf = &sdm845_perf_data,
> - .mdss_irqs = IRQ_SDM845_MASK,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR) | \
> + BIT(MDP_INTF2_INTR) | \
> + BIT(MDP_INTF3_INTR) | \
> + BIT(MDP_AD4_0_INTR) | \
> + BIT(MDP_AD4_1_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 33303040fbd0..a2c8b7c51890 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -83,7 +83,15 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
> .reg_dma_count = 1,
> .dma_cfg = &sm8150_regdma,
> .perf = &sm8150_perf_data,
> - .mdss_irqs = IRQ_SDM845_MASK,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR) | \
> + BIT(MDP_INTF2_INTR) | \
> + BIT(MDP_INTF3_INTR) | \
> + BIT(MDP_AD4_0_INTR) | \
> + BIT(MDP_AD4_1_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 48185e3dc873..26211f4fad99 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -75,7 +75,17 @@ static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
> .reg_dma_count = 1,
> .dma_cfg = &sm8150_regdma,
> .perf = &sc8180x_perf_data,
> - .mdss_irqs = IRQ_SC8180X_MASK,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR) | \
> + BIT(MDP_INTF2_INTR) | \
> + BIT(MDP_INTF3_INTR) | \
> + BIT(MDP_INTF4_INTR) | \
> + BIT(MDP_INTF5_INTR) | \
> + BIT(MDP_AD4_0_INTR) | \
> + BIT(MDP_AD4_1_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index 4e667c7e98e9..b3d3b6fb4412 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -231,7 +231,14 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
> .reg_dma_count = 1,
> .dma_cfg = &sm8250_regdma,
> .perf = &sm8250_perf_data,
> - .mdss_irqs = IRQ_SM8250_MASK,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR) | \
> + BIT(MDP_INTF2_INTR) | \
> + BIT(MDP_INTF3_INTR) | \
> + BIT(MDP_INTF4_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 7f998ffa195f..2c991cb6ed7a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -142,7 +142,11 @@ static const struct dpu_mdss_cfg sc7180_dpu_cfg = {
> .reg_dma_count = 1,
> .dma_cfg = &sdm845_regdma,
> .perf = &sc7180_perf_data,
> - .mdss_irqs = IRQ_SC7180_MASK,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index 7e4cfb0d6901..1ba646cb96a9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -82,7 +82,11 @@ static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> .perf = &sm6115_perf_data,
> - .mdss_irqs = IRQ_SC7180_MASK,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 440240860635..2d9b54ff6510 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -72,7 +72,11 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> .perf = &qcm2290_perf_data,
> - .mdss_irqs = IRQ_SC7180_MASK,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_INTR) | \
> + BIT(MDP_INTF1_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index b27f6c528a1f..3080f34d2e5e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -214,7 +214,13 @@ static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
> .reg_dma_count = 1,
> .dma_cfg = &sm8350_regdma,
> .perf = &sm8350_perf_data,
> - .mdss_irqs = IRQ_SM8350_MASK,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_7xxx_INTR) | \
> + BIT(MDP_INTF1_7xxx_INTR) | \
> + BIT(MDP_INTF2_7xxx_INTR) | \
> + BIT(MDP_INTF3_7xxx_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 3117bb358117..37b1f410e2c4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -148,7 +148,12 @@ static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
> .vbif = sdm845_vbif,
> .perf = &sc7280_perf_data,
> - .mdss_irqs = IRQ_SC7280_MASK,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_7xxx_INTR) | \
> + BIT(MDP_INTF1_7xxx_INTR) | \
> + BIT(MDP_INTF5_7xxx_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 81cbc99334a6..a023f4b1b92a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -100,7 +100,18 @@ static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = {
> .reg_dma_count = 1,
> .dma_cfg = &sc8280xp_regdma,
> .perf = &sc8280xp_perf_data,
> - .mdss_irqs = IRQ_SC8280XP_MASK,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_7xxx_INTR) | \
> + BIT(MDP_INTF1_7xxx_INTR) | \
> + BIT(MDP_INTF2_7xxx_INTR) | \
> + BIT(MDP_INTF3_7xxx_INTR) | \
> + BIT(MDP_INTF4_7xxx_INTR) | \
> + BIT(MDP_INTF5_7xxx_INTR) | \
> + BIT(MDP_INTF6_7xxx_INTR) | \
> + BIT(MDP_INTF7_7xxx_INTR) | \
> + BIT(MDP_INTF8_7xxx_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index a453c31c4bc7..2b6d48073bce 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -111,7 +111,13 @@ static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
> .reg_dma_count = 1,
> .dma_cfg = &sm8450_regdma,
> .perf = &sm8450_perf_data,
> - .mdss_irqs = IRQ_SM8450_MASK,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_7xxx_INTR) | \
> + BIT(MDP_INTF1_7xxx_INTR) | \
> + BIT(MDP_INTF2_7xxx_INTR) | \
> + BIT(MDP_INTF3_7xxx_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 1d74ea789b4d..c54b77f3c940 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -197,7 +197,13 @@ static const struct dpu_mdss_cfg sm8550_dpu_cfg = {
> .reg_dma_count = 1,
> .dma_cfg = &sm8450_regdma,
> .perf = &sm8450_perf_data,
> - .mdss_irqs = IRQ_SM8450_MASK,
> + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> + BIT(MDP_SSPP_TOP0_INTR2) | \
> + BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> + BIT(MDP_INTF0_7xxx_INTR) | \
> + BIT(MDP_INTF1_7xxx_INTR) | \
> + BIT(MDP_INTF2_7xxx_INTR) | \
> + BIT(MDP_INTF3_7xxx_INTR),
> };
>
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 3b015f3be31a..0b73e34d50a6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -83,79 +83,6 @@
>
> #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
>
> -#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_INTR) | \
> - BIT(MDP_INTF1_INTR) | \
> - BIT(MDP_INTF2_INTR) | \
> - BIT(MDP_INTF3_INTR) | \
> - BIT(MDP_AD4_0_INTR) | \
> - BIT(MDP_AD4_1_INTR))
> -
> -#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_INTR) | \
> - BIT(MDP_INTF1_INTR))
> -
> -#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_7xxx_INTR) | \
> - BIT(MDP_INTF1_7xxx_INTR) | \
> - BIT(MDP_INTF5_7xxx_INTR))
> -
> -#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_INTR) | \
> - BIT(MDP_INTF1_INTR) | \
> - BIT(MDP_INTF2_INTR) | \
> - BIT(MDP_INTF3_INTR) | \
> - BIT(MDP_INTF4_INTR))
> -
> -#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_7xxx_INTR) | \
> - BIT(MDP_INTF1_7xxx_INTR) | \
> - BIT(MDP_INTF2_7xxx_INTR) | \
> - BIT(MDP_INTF3_7xxx_INTR))
> -
> -#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_INTR) | \
> - BIT(MDP_INTF1_INTR) | \
> - BIT(MDP_INTF2_INTR) | \
> - BIT(MDP_INTF3_INTR) | \
> - BIT(MDP_INTF4_INTR) | \
> - BIT(MDP_INTF5_INTR) | \
> - BIT(MDP_AD4_0_INTR) | \
> - BIT(MDP_AD4_1_INTR))
> -
> -#define IRQ_SC8280XP_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_7xxx_INTR) | \
> - BIT(MDP_INTF1_7xxx_INTR) | \
> - BIT(MDP_INTF2_7xxx_INTR) | \
> - BIT(MDP_INTF3_7xxx_INTR) | \
> - BIT(MDP_INTF4_7xxx_INTR) | \
> - BIT(MDP_INTF5_7xxx_INTR) | \
> - BIT(MDP_INTF6_7xxx_INTR) | \
> - BIT(MDP_INTF7_7xxx_INTR) | \
> - BIT(MDP_INTF8_7xxx_INTR))
> -
> -#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
> - BIT(MDP_SSPP_TOP0_INTR2) | \
> - BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> - BIT(MDP_INTF0_7xxx_INTR) | \
> - BIT(MDP_INTF1_7xxx_INTR) | \
> - BIT(MDP_INTF2_7xxx_INTR) | \
> - BIT(MDP_INTF3_7xxx_INTR))
> -
> #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
> BIT(DPU_WB_UBWC) | \
> BIT(DPU_WB_YUV_CONFIG) | \
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