[Freedreno] [PATCH v11 7/9] drm/msm/dpu: separate DSC flush update out of interface

Kuogee Hsieh quic_khsieh at quicinc.com
Fri May 19 15:55:32 UTC 2023


On 5/18/2023 4:37 PM, Dmitry Baryshkov wrote:
> On 19/05/2023 02:33, Kuogee Hsieh wrote:
>> Currently DSC flushing happens during interface configuration at
>> dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from
>> dpu_hw_ctl_intf_cfg_v1() by adding 
>> dpu_hw_ctl_update_pending_flush_dsc_v1()
>> to handle both per-DSC engine and DSC flush bits at same time to make it
>> consistent with the location of flush programming of other DPU 
>> sub-blocks.
>>
>> Changes in v10:
>> -- rewording commit text
>> -- pass ctl directly instead of dpu_enc to dsc_pipe_cfg()
>> -- ctx->pending_dsc_flush_mask = 0;
>>
>> Changes in v11:
>> -- add Fixes tag
>> -- capitalize MERGE_3D, DSPP and DSC at struct dpu_hw_ctl_ops{}
>>
>> Fixes: 77f6da90487c ("drm/msm/disp/dpu1: Add DSC support in hw_ctl")
>
> NAK. The fix should be in a separate patch. This has been written 
> several times during the review.

yes, i know that. but i just intended to keep this patch at same order 
as before.

are you want me to move this patch to the first?


>
>> Signed-off-by: Kuogee Hsieh <quic_khsieh at quicinc.com>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 ++++++++--
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c  | 23 
>> +++++++++++++++++------
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h  | 13 +++++++++++++
>>   3 files changed, 38 insertions(+), 8 deletions(-)
>>
>


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