[Freedreno] [PATCH 3/6] drm/msm/dpu: split interrupt address arrays

[Dmitry Baryshkov]

On 22/05/2023 17:36, Neil Armstrong wrote:
> Hi,
> 
> On 22/05/2023 02:42, Dmitry Baryshkov wrote:
>> There is no point in having a single enum (and a single array) for both
>> DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
>> enum and two IRQ address arrays.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
>> ---
>>   .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  2 +
>>   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +++++++++++++------
>>   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ++++---
>>   3 files changed, 74 insertions(+), 38 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index 677048cc3b7d..72530ebb0ae6 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
>>    * @has_dim_layer      dim layer feature status
>>    * @has_idle_pc        indicate if idle power collapse feature is 
>> supported
>>    * @has_3d_merge       indicate if 3D merge is supported
>> + * @has_7xxx_intr      indicate that INTF/IRQs use addressing for DPU 
>> 7.0 and greater
>>    * @max_linewidth      max linewidth for sspp
>>    * @pixel_ram_size     size of latency hiding and de-tiling buffer 
>> in bytes
>>    * @max_hdeci_exp      max horizontal decimation supported (max is 
>> 2^value)
>> @@ -364,6 +365,7 @@ struct dpu_caps {
>>       bool has_dim_layer;
>>       bool has_idle_pc;
>>       bool has_3d_merge;
>> +    bool has_7xxx_intr;
> 
> looks good, but I can't find where has_7xxx_intr is set in the patchset
> 
> Neil

Indeed. It seems I missed a patch.

-- 
With best wishes
Dmitry