[Freedreno] [PATCH v12 07/10] drm/msm/dpu: always clear every individual pending flush mask

[Marijn Suijten]

On 2023-05-22 12:30:50, Kuogee Hsieh wrote:
> There are two tiers of pending flush control, main controller and
> individual hardware block. Currently only the main controller of

I would call "main controller" "top level" instead, but not sure how the
hardware manual calls this?

> flush mask is reset to 0 but leave out some individual pending flush
> mask of particular hardware block keep previous value at
> clear_pending_flush().

... but the individual pending flush masks of particular hardware blocks
are left at their previous values, eventually accumulating all possible
bit values and typically flushing more than necessary.

> Reset all individual hardware blocks flush
> mask to 0 to avoid individual hardware block be triggered accidentally.

maskS*

> 
> Signed-off-by: Kuogee Hsieh <quic_khsieh at quicinc.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>

Thanks!  Does this need any fixes tag?

Reviewed-by: Marijn Suijten <marijn.suijten at somainline.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 69d0ea2..069c6e5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -100,7 +100,9 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx)
>  	trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask,
>  				     dpu_hw_ctl_get_flush_register(ctx));
>  	ctx->pending_flush_mask = 0x0;
> -
> +	ctx->pending_intf_flush_mask = 0;
> +	ctx->pending_wb_flush_mask = 0;
> +	ctx->pending_merge_3d_flush_mask = 0;

I wouldn't mind keeping an empty line here.

>  	memset(ctx->pending_dspp_flush_mask, 0,
>  		sizeof(ctx->pending_dspp_flush_mask));
>  }
> -- 
> 2.7.4
>