[Freedreno] [PATCH 2/2] drm/msm/dpu: try multirect based on mdp clock limits

[Abhinav Kumar]

On 9/8/2023 4:30 PM, Dmitry Baryshkov wrote:
> On Fri, 8 Sept 2023 at 21:55, Abhinav Kumar <quic_abhinavk at quicinc.com> wrote:
>>
>> It's certainly possible that for large resolutions a single DPU SSPP
>> cannot process the image without exceeding the MDP clock limits but
>> it can still process it in multirect mode because the source rectangles
>> will get divided and can fall within the MDP clock limits.
>>
>> If the SSPP cannot process the image even in multirect mode, then it
>> will be rejected in dpu_plane_atomic_check_pipe().
>>
>> Hence try using multirect for resolutions which cannot be processed
>> by a single SSPP without exceeding the MDP clock limits.
>>
>> Signed-off-by: Abhinav Kumar <quic_abhinavk at quicinc.com>
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +++-
>>   1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> index 62dd9f9b4dce..85072328cd53 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>> @@ -792,6 +792,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
>>                                                                                   plane);
>>          int ret = 0, min_scale;
>>          struct dpu_plane *pdpu = to_dpu_plane(plane);
>> +       struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
>>          struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
>>          struct dpu_sw_pipe *pipe = &pstate->pipe;
>>          struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
>> @@ -860,7 +861,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
>>
>>          max_linewidth = pdpu->catalog->caps->max_linewidth;
>>
>> -       if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
>> +       if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) ||
>> +            _dpu_plane_calc_clk(&crtc_state->mode, pipe_cfg) > kms->perf.max_core_clk_rate) {
> 
> First, I think this should be an adjusted_mode too. And this probably
> needs some more attention in the next few lines of code, since .e.g
> the UBWC case also needs to be adjusted.
> 

Ack, will change this to adjusted_mode as well

Yes, need to update UBWC check like below, thanks for catching it.

@@ -869,7 +878,7 @@ static int dpu_plane_atomic_check(struct drm_plane 
*plane,
                  * full width is more than max_linewidth, thus each rect is
                  * wider than allowed.
                  */
-               if (DPU_FORMAT_IS_UBWC(fmt)) {
+               if (DPU_FORMAT_IS_UBWC(fmt) && 
drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
                         DPU_DEBUG_PLANE(pdpu, "invalid src " 
DRM_RECT_FMT " line:%u, tiled format\n",
 
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
                         return -E2BIG;

>>                  /*
>>                   * In parallel multirect case only the half of the usual width
>>                   * is supported for tiled formats. If we are here, we know that
>> --
>> 2.40.1
>>
> 
>