[PATCH v2] drm/msm/dp: fix the max supported bpp logic

[Stephen Boyd]

Quoting Abhinav Kumar (2024-07-30 10:55:40)
> Fix the dp_panel_get_supported_bpp() API to return the minimum
> supported bpp correctly for relevant cases and use this API
> to correct the behavior of DP driver which hard-codes the max supported
> bpp to 30.
>
> This is incorrect because the number of lanes and max data rate
> supported by the lanes need to be taken into account.
>
> Replace the hardcoded limit with the appropriate math which accounts
> for the accurate number of lanes and max data rate.
>
> changes in v2:
>         - Fix the dp_panel_get_supported_bpp() and use it
>         - Drop the max_t usage as dp_panel_get_supported_bpp() already
>           returns the min_bpp correctly now
>
> Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support")
> Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/43
> Reported-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> Tested-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org> # SM8350-HDK
> Signed-off-by: Stephen Boyd <swboyd at chromium.org>
> Signed-off-by: Abhinav Kumar <quic_abhinavk at quicinc.com>
> ---

One note below,

Reviewed-by: Stephen Boyd <swboyd at chromium.org>

> diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
> index a916b5f3b317..3777b1abacad 100644
> --- a/drivers/gpu/drm/msm/dp/dp_panel.c
> +++ b/drivers/gpu/drm/msm/dp/dp_panel.c
> @@ -90,22 +90,22 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
>  static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel,
>                 u32 mode_edid_bpp, u32 mode_pclk_khz)
>  {
> -       struct dp_link_info *link_info;
> +       const struct dp_link_info *link_info;
>         const u32 max_supported_bpp = 30, min_supported_bpp = 18;
> -       u32 bpp = 0, data_rate_khz = 0;
> +       u32 bpp, data_rate_khz;
>
>         bpp = min_t(u32, mode_edid_bpp, max_supported_bpp);

This can be min() because all types are u32.

>
>         link_info = &dp_panel->link_info;
>         data_rate_khz = link_info->num_lanes * link_info->rate * 8;
>
> -       while (bpp > min_supported_bpp) {
> +       do {
>                 if (mode_pclk_khz * bpp <= data_rate_khz)
> -                       break;
> +                       return bpp;
>                 bpp -= 6;
> -       }
> +       } while (bpp > min_supported_bpp);
>
> -       return bpp;
> +       return min_supported_bpp;
>  }
>
>  int dp_panel_read_sink_caps(struct dp_panel *dp_panel,