[PATCH v2 3/3] drm/msm: Fix CP_BV_DRAW_STATE_ADDR name

[Akhil P Oommen]

On Wed, Aug 07, 2024 at 01:34:29PM +0100, Connor Abbott wrote:
> This was missed because we weren't using the a750-specific indexed regs.
> 
> Fixes: f3f8207d8aed ("drm/msm: Add devcoredump support for a750")
> Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>

Reviewed-by: Akhil P Oommen <quic_akhilpo at quicinc.com>

-Akhil

> ---
>  drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h
> index 260d66eccfec..9a327d543f27 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h
> @@ -1303,7 +1303,7 @@ static struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = {
>  		REG_A6XX_CP_ROQ_DBG_DATA, 0x00800},
>  	{ "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
>  		REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x08000},
> -	{ "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
> +	{ "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
>  		REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x00200},
>  	{ "CP_BV_ROQ_DBG_ADDR", REG_A7XX_CP_BV_ROQ_DBG_ADDR,
>  		REG_A7XX_CP_BV_ROQ_DBG_DATA, 0x00800},
> 
> -- 
> 2.31.1
> 
>