[PATCH v3] drm/msm/adreno: Add A306A support

[Barnabás Czémán]

I hope it was not forgotten or am I missing something?

On Mon, Jul 22, 2024 at 4:58 PM Barnabás Czémán <trabarni at gmail.com> wrote:
>
> From: Otto Pflüger <otto.pflueger at abscue.de>
>
> Add support for Adreno 306A GPU what is found in MSM8917 SoC.
> This GPU marketing name is Adreno 308.
>
> Signed-off-by: Otto Pflüger <otto.pflueger at abscue.de>
> [use internal name of the GPU, reword the commit message]
> Reviewed-by: Konrad Dybcio <konrad.dybcio at linaro.org>
> Signed-off-by: Barnabás Czémán <trabarni at gmail.com>
> ---
> Changes in v3:
> - Fix issues addressed by reviews.
> - Rebase on latest next.
> - Link to v2: https://lore.kernel.org/r/20240620-a306a-v2-1-0d388e1deebf@gmail.com
>
> Changes in v2:
> - Rebase on https://patchwork.freedesktop.org/series/127393/
> - Link to v1: https://lore.kernel.org/r/20240528-a306a-v1-1-03a66dacd8c7@gmail.com
> ---
>  drivers/gpu/drm/msm/adreno/a3xx_catalog.c | 11 +++++++++++
>  drivers/gpu/drm/msm/adreno/a3xx_gpu.c     | 14 +++++++++++---
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h   |  6 ++++++
>  3 files changed, 28 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
> index 0de8465b6cf0..2eb6c3e93748 100644
> --- a/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a3xx_catalog.c
> @@ -41,6 +41,17 @@ static const struct adreno_info a3xx_gpus[] = {
>                 .gmem  = SZ_128K,
>                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
>                 .init  = a3xx_gpu_init,
> +       }, {
> +               .chip_ids = ADRENO_CHIP_IDS(0x03000620),
> +               .family = ADRENO_3XX,
> +               .revn = 308,
> +               .fw = {
> +                       [ADRENO_FW_PM4] = "a300_pm4.fw",
> +                       [ADRENO_FW_PFP] = "a300_pfp.fw",
> +               },
> +               .gmem = SZ_128K,
> +               .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> +               .init = a3xx_gpu_init,
>         }, {
>                 .chip_ids = ADRENO_CHIP_IDS(
>                         0x03020000,
> diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> index 5273dc849838..b46ff49f47cf 100644
> --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> @@ -145,6 +145,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
>                 gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
>                 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);
>                 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a);
> +       } else if (adreno_is_a306a(adreno_gpu)) {
> +               gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
> +               gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000010);
> +               gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000010);
>         } else if (adreno_is_a320(adreno_gpu)) {
>                 /* Set up 16 deep read/write request queues: */
>                 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
> @@ -237,7 +241,9 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
>         gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
>
>         /* Enable Clock gating: */
> -       if (adreno_is_a305b(adreno_gpu) || adreno_is_a306(adreno_gpu))
> +       if (adreno_is_a305b(adreno_gpu) ||
> +           adreno_is_a306(adreno_gpu) ||
> +           adreno_is_a306a(adreno_gpu))
>                 gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
>         else if (adreno_is_a320(adreno_gpu))
>                 gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
> @@ -334,8 +340,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
>                 gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);
>
>         /* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
> -       if (adreno_is_a305(adreno_gpu) || adreno_is_a306(adreno_gpu) ||
> -                       adreno_is_a320(adreno_gpu)) {
> +       if (adreno_is_a305(adreno_gpu) ||
> +           adreno_is_a306(adreno_gpu) ||
> +           adreno_is_a306a(adreno_gpu) ||
> +           adreno_is_a320(adreno_gpu)) {
>                 gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,
>                                 AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
>                                 AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 1ab523a163a0..c3b7970c2bfa 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -294,6 +294,12 @@ static inline bool adreno_is_a306(const struct adreno_gpu *gpu)
>         return adreno_is_revn(gpu, 307);
>  }
>
> +static inline bool adreno_is_a306a(const struct adreno_gpu *gpu)
> +{
> +       /* a306a (marketing name is a308) */
> +       return adreno_is_revn(gpu, 308);
> +}
> +
>  static inline bool adreno_is_a320(const struct adreno_gpu *gpu)
>  {
>         return adreno_is_revn(gpu, 320);
>
> ---
> base-commit: dee7f101b64219f512bb2f842227bd04c14efe30
> change-id: 20240528-a306a-48e173724d6c
>
> Best regards,
> --
> Barnabás Czémán <trabarni at gmail.com>
>