[PATCH 01/21] drm/msm/dsi: add support to DSI CTRL v2.8.0

[Dmitry Baryshkov]

On Thu, 29 Aug 2024 at 13:19, Jun Nie <jun.nie at linaro.org> wrote:
>
> From: Jonathan Marek <jonathan at marek.ca>
>
> Add support to DSI CTRL v2.8.0 with priority support

Proper description is missing

>
> Signed-off-by: Jun Nie <jun.nie at linaro.org>

Several tags are missing here.

Also, how is this patch related to quadpipe?

> ---
>  drivers/gpu/drm/msm/dsi/dsi_host.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 185d7de0bf376..6388bb12696ff 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -2238,13 +2238,23 @@ int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
>         return ret;
>  }
>
> +#define DSI_VBIF_CTRL                  (0x01CC - 4)
> +#define DSI_VBIF_CTRL_PRIORITY         0x07
> +
>  void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
>                                   u32 len)
>  {
>         struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> +       const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
> +       u32 reg;
>
>         dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
>         dsi_write(msm_host, REG_DSI_DMA_LEN, len);
> +       if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_8_0) {
> +               reg = dsi_read(msm_host, DSI_VBIF_CTRL);
> +               reg |= (DSI_VBIF_CTRL_PRIORITY & 0x7);
> +               dsi_write(msm_host, DSI_VBIF_CTRL, reg);
> +       }
>         dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
>
>         /* Make sure trigger happens */
>
> --
> 2.34.1
>


-- 
With best wishes
Dmitry