[PATCH v2 4/9] drm/msm/A6xx: Implement preemption for A7XX targets

[Rob Clark]

On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco
<antomani103 at gmail.com> wrote:
>
> This patch implements preemption feature for A6xx targets, this allows
> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX
> hardware as such supports multiple levels of preemption granularities,
> ranging from coarse grained(ringbuffer level) to a more fine grained
> such as draw-call level or a bin boundary level preemption. This patch
> enables the basic preemption level, with more fine grained preemption
> support to follow.
>
> Signed-off-by: Sharat Masetty <smasetty at codeaurora.org>
> Signed-off-by: Antonino Maniscalco <antomani103 at gmail.com>
> Tested-by: Neil Armstrong <neil.armstrong at linaro.org> # on SM8650-QRD
> ---
>  drivers/gpu/drm/msm/Makefile              |   1 +
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c     | 323 +++++++++++++++++++++-
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.h     | 168 ++++++++++++
>  drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 431 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/msm/msm_ringbuffer.h      |   7 +
>  5 files changed, 921 insertions(+), 9 deletions(-)
>

[snip]

> +
> +int a6xx_preempt_submitqueue_setup(struct msm_gpu *gpu,
> +               struct msm_gpu_submitqueue *queue)
> +{
> +       void *ptr;
> +
> +       /*
> +        * Create a per submitqueue buffer for the CP to save and restore user
> +        * specific information such as the VPC streamout data.
> +        */
> +       ptr = msm_gem_kernel_new(gpu->dev, A6XX_PREEMPT_USER_RECORD_SIZE,
> +                       MSM_BO_WC, gpu->aspace, &queue->bo, &queue->bo_iova);

Can this be MSM_BO_MAP_PRIV?  Otherwise it is visible (and writeable)
by other proceess's userspace generated cmdstream.

And a similar question for the scratch_bo..  I'd have to give some
thought to what sort of mischief could be had, but generall kernel
mappings that are not MAP_PRIV are a thing to be careful about.

BR,
-R