[PATCH v2 15/19] drm/msm/dp: enable SDP and SDE periph flush update

[Abhinav Kumar]

On 2/10/2024 2:11 PM, Dmitry Baryshkov wrote:
> On Sat, 10 Feb 2024 at 23:49, Abhinav Kumar <quic_abhinavk at quicinc.com> wrote:
>>
>>
>>
>> On 2/10/2024 2:16 AM, Dmitry Baryshkov wrote:
>>> On Sat, 10 Feb 2024 at 03:52, Paloma Arellano <quic_parellan at quicinc.com> wrote:
>>>>
>>>> DP controller can be setup to operate in either SDP update flush mode or
>>>> peripheral flush mode based on the DP controller hardware version.
>>>>
>>>> Starting in DP v1.2, the hardware documents require the use of
>>>> peripheral flush mode for SDP packets such as PPS OR VSC SDP packets.
>>>>
>>>> In-line with this guidance, lets program the DP controller to use
>>>> peripheral flush mode starting DP v1.2
>>>>
>>>> Changes in v2:
>>>>           - Use the original dp_catalog_hw_revision() function to
>>>>             correctly check the DP HW version
>>>>
>>>> Signed-off-by: Paloma Arellano <quic_parellan at quicinc.com>
>>>> ---
>>>>    drivers/gpu/drm/msm/dp/dp_catalog.c | 17 +++++++++++++++++
>>>>    drivers/gpu/drm/msm/dp/dp_catalog.h |  1 +
>>>>    drivers/gpu/drm/msm/dp/dp_ctrl.c    |  1 +
>>>>    drivers/gpu/drm/msm/dp/dp_reg.h     |  2 ++
>>>>    4 files changed, 21 insertions(+)
>>>>
>>
>> <Snip>
>>
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
>>>> index 2983756c125cd..6ac66532b47a4 100644
>>>> --- a/drivers/gpu/drm/msm/dp/dp_reg.h
>>>> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h
>>>> @@ -102,6 +102,8 @@
>>>>    #define DP_MAINLINK_CTRL_ENABLE                        (0x00000001)
>>>>    #define DP_MAINLINK_CTRL_RESET                 (0x00000002)
>>>>    #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER   (0x00000010)
>>>> +#define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP      (0x00800000)
>>>> +#define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE       (0x01800000)
>>>
>>> Just one bit here, please.
>>>
>>
>> hmm .... so the periph flush bits are 24:23 and we need a value of 3 to
>> select peripheral flush which translates to 0x01800000.
>>
>> How do you suggest to break this up?
> 
> Then FIELD_PREP(something_mask, 3). Otherwise it is too easy to
> consider it to be DP_MAINLINK_FLUSH_MODE_UPDATE_SDP | BIT(24)
> 

Sure, FIELD_PREP() works. I was confused when you said one bit :)

>>
>>>>    #define DP_MAINLINK_FB_BOUNDARY_SEL            (0x02000000)
>>>>
>>>>    #define REG_DP_STATE_CTRL                      (0x00000004)
>>>> --
>>>> 2.39.2
>>>>
>>>
>>>
> 
> 
>